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part number 405exr revision 1.10 - july 10, 2008 amcc proprietary 1 405exr powerpc 405exr embedded processor preliminary data sheet features ? amcc powerpc ? 405 32-bit risc processor core operating from 333mhz to 533mhz including 16kb i- and d-caches with parity checking ? on-chip 128-bit processor local bus (plb) operating up to 200mhz ? on-chip 32-bit peripheral bus (opb) operating up to 100 mhz ? external 8-,16-, or 32-bit peripheral bus (ebc) operating up to 100mhz ? external bus master (ebm) operating up to 100mhz ? on-chip security feature with true random number generation ? eight- and 16-bit nand flash interface ? inter-chip connectivity (scp and iic) ? boot from nor flash on the external peripheral bus or nand flash on the nand flash interface ? dma (4-channel) support for all on-chip slaves and external bus, uarts, and devices on the ebc ? ddr1/2 sdram interface operating up to 400 mbps ? one one-lane pci express interfaces operating up to 2.5 gbps ? one gigabit ethernet interfaces (half- and full- duplex) to external phy (gmii/mii/rgmii) ? usb 2.0 otg port configurable as either host or device ? programmable universal interrupt controller (uic) ? general purpose timer (gpt) ? up to two serial ports (16750 compatible uart) ? two iic interfaces operating up to 400khz and supporting all standard iic eeproms ? one scp (spi) synchronous full-duplex channel operating up to 25 mhz ? general purpose i/os (gpios), each with programmable interrupts and outputs ? supports jtag for board-level testing ? system power mana gement, low power dissipation and small form factor ? available in a rohs comp liant (lead-free) package description with speeds up to 533mhz, a flexible off-chip memory architecture, and a diverse communications package that includes pci express, usb 2.0 otg, and 10/100/1000 ethernet, the powerpc 405exr embedded processor provides a low power and small footprint system-on-a-chip (soc) solution for a wide range of high performance, cost-constrained embedded applications. this includes wireless lan applications, security appliances, internet appliances, line cards, and intelligent u sb peripherals. it is an easily programmable general purpose, 32-bit risc controller that offers an upgrade path for applications in need of performance and connectivity improvements. technology: cu-08 cmos, 90nm package: 388-ball, 27mm 27mm, enhanced plastic ball grid array (epbga), 1mm ball pitch power consumption: typically less than 2w at all speeds voltages required: 3.3v, 2.5v, 1.8v (ddr2 sdram only), and 1.2v
ppc405exr ? powerpc 405exr embedded processor 2 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering, pvr, and jtag informat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 powerpc 405 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nand flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 usb 2.0 otg interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ddr1/2 sdram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 security function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial communication port interface (scp/ spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general purpose i/o (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 signal functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ratings and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ddr 2/1 sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 pci express (pci-e) i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 3 preliminary data sheet list of figures figure 1 . ppc405exr embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2 . package 27mm, 388-ball epbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3 . clocking waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 4 . input setup and hold timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 5 . output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6 . input setup and hold timing wa veform for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 7 . output delay and hold timing waveform for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 8 . ddr sdram simulation signal termination mo del . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 9 . ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 10 . ddr sdram read data path for a single data bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 figure 11 . ddr sdram memory data and dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 12 . ddr sdram read cycle timing?example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ppc405exr ? powerpc 405exr embedded processor 4 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet list of tables table 1 . system memory address map (4gb system memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2 . dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3 . signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 . signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5 . pin groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6 . non-functional ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7 . signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8 . absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9 . package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 10 . recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 11 . i/o input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12 . typical dc power supply requirements with ddr1 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 13 . maximum dc power supply requirements with ddr1 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14 . typical dc power supply requirements with ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 15 . maximum dc power supply requirements with ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 16 . dc power supply loads with ddr1 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 17 . dc power supply loads with ddr2 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18 . power contribution of functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19 . system clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20 . peripheral interface i/o clock timings (not sdram or pci-e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21 . i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 22 . ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23 . ddr sdram write operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 24 . i/o timing?ddr sdram t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 25 . i/o timing?ddr sdram t sa and t ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 26 . i/o timing?ddr sdram write timing t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 27 . i/o timing?ddr sdram read timing t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 28 . pci-e receiver i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 29 . pci-e reference clock i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 30 . pci-e transmitter i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 31 . strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 5 preliminary data sheet ordering, pvr, and jtag information this section provides the part number nomenclature. fo r availability, contact your local amcc sales office. the part number contains a part modifier . included in the modifier is a revisi on code. this refers to the die mask revision number and is specified in the part num bering scheme for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. see the ppc405exr embedded processor user?s manual for details about accessing these registers. order part number key product name order part number ( see notes:) package rev level pvr value jtag id ppc405exr ppc405exr-spcffft 27mm, 388-ball, epbga c 0x1291147b 0x1405b1e1 ppc405exr ppc405exr-npcffft 27mm, 388-ball, epbga c 0x12911479 0x1405b1e1 notes: 1. s = security feature present, n = security feature not present 2. p = package: s = lead-free (rohs compliant), p = leaded 3. c = chip revision level c 4. fff = processor frequency 333 = 333mhz 400 = 400mhz 533 = 533mhz 5. t = case temperature range, -40 c to +85 c (see footnote 5. on page 51) amcc part number ppc405exr-ssb533t chip package processor speed (mhz) security case temperature range revision level note: the example p/n above has the security featur e, is lead-free, cap able of running at 533mhz, and is shipped in a tray (tape-and-reel packaging is not available).
ppc405exr ? powerpc 405exr embedded processor 6 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet block diagram figure 1. ppc405exr embedded controller functional block diagram the ppc405exr is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated together to create an asic (applicat ion-specific integrated circui t) product. this approach provides a consistent way to creat e complex asics using ibm coreconnect tm bus architecture. dcr gpio iicx2/ mal/w ethernet dma bridges clock control reset power mgmt jtag trace timers mmu controller opb/plb arbiter (4-channel) dcrs arbiter uart x2 scp (spi) 16kb i-cache 16kb d-cache on-chip peripheral bus (opb) processor local bus (plb4)?128 bits power pc 405 processor 1gbit bus bsc mac interrupt controller universal x3 security feature interrupt coalescing usb 2.0 controller nand flash controller eip-94 sdram controller ddr1/2 otg ulpi gpt ebm ebc hss pci-e pka trng ahb-plb bridge 1-lane
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 7 preliminary data sheet address maps the ppc405exr incorporates two address maps. the first address map defines the possible use of addressable memory regions that the processor can access. the seco nd address map defines device configuration register (dcr) addresses (numbers). the dcrs are accessed by software running on the ppc405exr processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (4gb system memory) function subfunction start address (hex) end address (hex) size local memory ddr 2/1 sdram 0 0000 0000 0 7fff ffff 2gb ebc 0 8000 0000 0 8fff ffff 256mb pci express 0 9000 0000 0 ef5f ffff 1.5gb opb peripherals gpt 0 ef60 0000 0 ef60 01ff 512b uart 0 0 ef60 0200 0 ef60 0207 8b reserved 0 ef60 0208 0 ef60 02ff 248b uart 1 0 ef60 0300 0 ef60 0307 8b reserved 0 ef60 0308 0 ef60 03ff 248b iic 0 0 ef60 0400 0 ef60 041f 32b reserved 0 ef60 0420 0 ef60 04ff 224b iic 1 0 ef60 0500 0 ef60 051f 32b reserved 0 ef60 0520 0 ef60 05ff 224b scp 0 ef60 0600 0 ef60 0605 6b reserved 0 ef60 0606 0 ef60 06ff 250b opb arbiter 0 ef60 0700 0 ef60 073f 64b reserved 0 ef60 0740 0 ef60 07ff 192b gpio 0 ef60 0800 0 ef60 087f 128b reserved 0 ef60 0880 0 ef60 08ff 128b ethernet 0 0 ef60 0900 0 ef60 09ff 256b reserved 0 ef60 0a00 0 ef60 0aff 256b rgmii bridge 0 ef60 0b00 0 ef60 0c03 260b reserved 0 ef60 0c04 0 ef60 ffff 62kb plb/ahb peripherals pka +trng 0 ef61 0000 0 ef61 ffff 64kb pci express interrupt handler 0 ef62 0000 0 ef62 00ff 256b reserved 0 ef62 0100 0 ef6b ffff 640kb usb otg 0 ef6c 0000 0 ef6f ffff 256kb security 0 ef70 0000 0 ef77 ffff 512kb reserved 0 ef78 0000 0 efff ffff 8.9mb ebc ebc memory 0 f000 0000 0 ffdf ffff 254mb ebc memory?boot rom 0 ffe0 0000 0 ffff ffff 2mb notes: 1. if peripheral bus boot is selected, peripheral bank 0 is au tomatically configured at reset to the address range listed above. 2. after the boot process, software may reas sign the boot memory regions for other uses. 3. pci express can use plb address range 0x1 0000 0000 to 0xf ffff ffff even though the cpu can not access it.
ppc405exr ? powerpc 405exr embedded processor 8 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table 2. dcr address map function start address (hex) end address (hex) size total dcr address space 1 0x000 0x3ff 1kw (4kb) 1 reserved 000 00b cpr (clocking power-on reset) 00c 00d 2w system dcrs 00e 00f 2w ddr 2/1 sdram controller 010 011 2w external bus controller (ebc) 012 013 2w external bus master (ebm) 014 015 2w reserved 016 01f plb4xahb bridge 020 02f 16w reserved 030 03f pci express 0 040 05f 32w reserved 060 07f plb4 arbiter 080 08f 16w plb-to-opb bridge 090 09f 16w opb-to-plb bridge 0a0 0a7 8w reserved 0a8 0af power management 0b0 0b2 3w reserved 0b3 0bf uic 0 0c0 0cf 16w uic 1 0d0 0df 16w uic 2 0e0 0ef 16w reserved 0f0 0ff dma 100 13f 64w reserved 140 17f ethernet mal 180 1ff 128w reserved 200 3ff notes: 1. a dcr address is 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or o ne kiloword (kw) (which equals 4kb).
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 9 preliminary data sheet powerpc 405 processor the ppc405 processor is a fixed-point, 32-bit risc unit. features include: ? five-stage pipeline with single-cycle execution of most instructions, in cluding loads and stores ? separate, configurable 16 kb d- and i-caches, both two-way set associative ? thirty-two 32-bit general purpose registers (gprs) ? unaligned load/store support ? hardware multiply/divide ? parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (tlb) ? double word instruction fetch from cache ? translation of the four gb logical address space into physical addresses ? built-in timer and debug support ? power management ? dcr interface is 32 bits wide ? selectable processor vs. bus clock ratios (n:1 ratio only, where n =1, 2, 3,or 4 ) internal buses the ppc405exr contains four internal buses: the proces sor local bus (plb), the advanced high-performance bus (ahb), the on-chip peripheral bus (o pb), and the device control register (dcr) bus. hi gh performance devices such as the processor, the ddr sdram memory controller, pci expre ss, the ethernet ma l, and dma utilize the plb. lower bandwidth i/o in terfaces such as communications and time r interfaces utilize the opb. the daisy- chained dcr bus provides a lower bandwidth path for passing status and contro l information between the processor and the other on-chip peripheral functions. plb the processor local bus (plb) is a high-performance on-chip bus used to connect plb-equipped master and slave devices to the ppc405 cpu. it provides a 128-bit data path with 64-bit addressing and operates up to 200mhz. there are bridges between the plb and the opb. features include: ? separate and simultaneous 6.4gb/s read and write data paths ? decoupled address and data buses ? address pipelining ? late master request abort capability ? hidden (overlapped) bus request/grant protocol ? bus arbitration-locking mechanism ? byte-enable capabilit y allows for unaligned half wo rd transfers and 3-b transfers ? support for 32- and 64-b burst transfers ? read word address capability ? sequential burst protocol ? guarded and unguarded memory transfers ? simultaneous control, address, and data phases ? dma buffered, flyby, peripheral-to-memory, memory-to-peripheral, and dma memory-to-memory operations ahb the advanced high-performance bus (ahb) is dedicated to the usb otg 2.0. features include: ? 32-bit data path ? 32-bit address ? synchronous to the plb ? from 60mhz to 100mhz.
ppc405exr ? powerpc 405exr embedded processor 10 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet opb the opb provides 32-bit address and data interfaces, and operates up to 100mhz. there are bridges between the opb and the plb. features include: ? pipelined read support ? dynamic bus sizing ? single-cycle data transfer between masters and slaves dcr bus the daisy-chained dcr bus provides a path for passing st atus and control information between the processor core and the other on-chip cores. all dcrs are 32 bits in width with 10-bit addressing. external bus controller the external bus controller (ebc and ebm) transfers data between the plb and external memory or peripheral devices attached to the external peripheral bus. the ebc provides direct attachment of memory devices such as rom and sram, dma device paced memory devices, and dma peripheral devices. features include: ? up to 33mhz to 100 mhz speed ? data bus is 8, 16, or 32 bits with a 27-bit address bus ? up to four chip selects ? arbitration and multi-master supported ? flash rom interface ? boot from 8- or 16-bit nor flash support ? direct support for 8-,16-, or 32-bit sram and external peripherals ? external bus master support nand flash controller the nand flash controller (ndfc) prov ides a simple interface between the external bus controller (ebc) and a variety of nand flash-based storage devices. features include: ? attachment as internal ebc slave device ? eight- and 16-bit nand flash interface ? up to four banks of nand flash supported ? device sizes: ? 4mb and larger supporte d for read/w rite access ? 4mb to 256mb supported for boot-from-nand fl ash (size supported depends on addressing mode) ? 512b + 16b or 2kb + 64b device page sizes supported ? ecc generation - hamming code, single-bit correction, double-bit detection (sec/ded) ? eight-bit command write, address write, and data read/write ? interrupt on device ready (after long page write or block erase operations) ? boot from nand ? executes up to 4kb of boot code out of first block ? automatic page read accesses performed based on device configuration and read address dma controller the direct memory access (dma) controller is a processo r local bus (plb) master that enables faster data transfer between memory and peripherals than is possib le under program control. the 4-channel dma controller handles data transfers between memory and peripherals and from memory-to-memory. each channel has an
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 11 preliminary data sheet independent set of registers needed for data transfer: a c ontrol register, a source address register, a destination address register, and a transfer count register. features include: ? memory-to-memory transfers ? buffered memory-to-peripheral transfers ? buffered peripheral-to-memory transfers ? four independent dma channels ? scatter/gather capability for dynamically programming multip le dma transfers ? programmable address increment or decrement ? internal data buffering ? can transfer data to/from any plb slave, including the external bus usb 2.0 otg interface one usb 2.0 on-the-go (otg) controller that can be configured as either a host or device port. features include: ? low- (host only), full- and high-speed support ? internal dma to optimize performance and offload the cpu ? up to two in/out endpoints in device mode (one can be isochronous) ? supports maximum packet size of 1024b (isochronous) and 512b (bulk) ? support for isochronous traffic ? three packets per microframe (24mb/s throughput) ? eight kb buffer ? ulpi sdr interface ddr1/2 sdram controller the double data rate 1/2 (ddr1/2) sdram memory contro ller supports industry standard discrete devices that are compatible with both the ddr1 or ddr2 specifications. the correct i/o supply voltage must be provided for the two types of ddr devices: ddr1 devices re quire +2.5v and ddr2 devices require +1.8v. global memory timings, address and bank sizes, and memory addressing modes are programmable. features include: ? 16- or 32-bit memory interface ? optional 8-bit error checking and correcting (ecc) ? 1.6-gb/s peak data rate ? two memory banks of up to 1 gb each ? maximum capacity of 2gb ? support for one memory bank of 2gb with cas latencies of 2, 2.5, or 3 ? clock frequencies from 133mhz (266mbps) to 200mhz (400mbps) supported (faster parts may be used, but must be clocked no faster than 200mhz) ? page mode accesses (up to 16 open pages) with configurable paging policy ? programmable address mapping and timing ? software initia ted self-refresh ? power management (self-refresh, suspend) ? two regions (two chip se lects, one clock driver)
ppc405exr ? powerpc 405exr embedded processor 12 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet pci express the pci express single-lane interfac e include the following features: features include: ? compliant with pci express base specification 1.1 ? port can be end point or root complex. (upstream & downstream) ? pci-express to pci-express opaque (non-transparent) bridge ? power management ? supports one virtual channel (vc0) with no traffic class (tc) filtering ? maximum payload block size 256b ? supports up to 512b maximum read request size ? requests supported: ? up to two posted outbound write requests (memory and messages) ? up to two posted inbound write requests ? up to two outbound read requests outstanding on pci express ? up to two inbound read requests outstanding on pci express ? outbound i/o request as a pci express root port ? inbound i/o request as a pci express end point ? buffering in pci express port for the following transaction types: ? 1kb replay buffer: up to eight in flight transactions ? 512b for outbound posted writes ? 512b for outbound reads completion ? 512b for inbound posted writes ? 512b for inbound reads completion ? parity checking on each buffer ? pom programmable outbound memory regions: 3 memory , 1 i/o, 1 message, 1 config, 1 internal regs ? pim programmable inbound memory region s: 4 memory, 1 i/o, 1 expansion rom ? intx interrupts support (pci legacy): ? up to four intx termination for root port s. a/b/c/d interrupts are wired to the uic ? a/b/c/d intx types generation for endpoints ? msi - message signaled interrupts ? msi generation for end point ? msi termination for root ports ? msi_x termination for root ports security function the built-in security function is a cryptographic engine a ttached to the 128-bit plb with built-in dma and interrupt controllers. features include: ? federal information processing standard (fips) 140-2 design ? support for an unlimited number of security associations (sa) ? different sa formats for each supported protocol (ipsec, ssl/tls/dtls, macsec, sgt l2/l3 and srtp) ? internet protocol security (ipsec) features ? full packet tran sforms (esp & ah) ? complete header and trailer processing (ipv4 and ipv6) ? multi-mode automatic padding ? "mutable bit" handler for ah, including ipv4 option and ipv6 extension headers ? secure socket layer (ssl), transport layer security (tls), and datagram transport layer security (dtls) ? packet transforms ? one-pass hash-then-encrypt or decrypt-then-hash for ssl, tls and dtls packet transforms using arc4 stream cipher
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 13 preliminary data sheet ? secure real-time protocol (srtp) features ? packet transforms ? roc removal and tag insertion ? variable bypass offset of header length per packet ? media access control security (macsec) features ? cipher suit e gcm-aes-128 ? header insertion and removal ? integrity and confidentiality with msdu ? sgt l2 supported features: ? gcm-aes with 128-bit key. ? integrity only and with confidentiality of msdu ? icv generation and validation sgt l3 supported features ? aes-gcm, aes-gmac with 12 8, 192 and 256 bit key. ? ipsec/ssl security acceleration engine ? des, 3des, aes, arc-4, aes-gcm, an d gmac-aes encryp tion/decryption ? md-5, sha-1, and sha-256 hashing ? public key acceleration for rsa, dsa and diffie-hellman ? combined encryption-hash and hash-decryption with the aes-ccm algorithm. ? true or pseudo random number generators ? non-deterministic true random numbers ? pseudo random numbers with lengths of 8b or 16b ? ansi x9.17 annex c compliant using a des algorithm ? interrupt controller ? fifteen programmable, maskable interrupts ? initiate commands via an input interrupt ? sixteen programmable interrupts indicating completion of certain operations ? all interrupts mapped to one level- or edge-sensitive programmable interrupt output ? dma controller ? autonomous, 4-channel ? 1024-words (32 bits/word) per dma transfer ? scatter/gather capability wit h byte aligned addressing ? byte reverse capability on sa and descriptors uart the universal asynchronous receiver/transmitter (uart) interface provides four configurations: ? one 8-signal port ? two 4-signal ports. ? two 2-signal ports ? one 4-signal port and one 2-signal port the uart performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. features include: ? compatible with the16750 ? all six software modem control functions (cts, rts, dsr, dtr, ri, dcd) on uart0 ? programmable auto flow (data flow controlled by rts and cts signals) ? characters can be 5, 6, 7, or 8 bits ? programmable start, stop, parity bit insertion ? sixty-four byte fifos for buffering tx and rx data ? lin sub-bus specification compliant - line break generation/detection and false start bit detection ? programmable internal/ext ernal loopback capabilities ? low power and sleep mode ? register conformance (after reset) to configuration of the ns16450 register set
ppc405exr ? powerpc 405exr embedded processor 14 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet ? hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) ? complete status reporting ? full prioritized inte rrupt system controls ? independently controlled transmit, receiv e, line status, and data set interrupts ? programmable baud generator (divides seri al clock input and generates 16x clock) ? ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data ? even, odd, or no-parity bit generation and detection ? stop bit generation of 1, 1.5, or 2 bits ? variable baud rate ? internal diagnostic capability ? loopback controls for isolating communications link faults ? break, parity, overrun, framing error simulation ? opb interface with optional dma support iic bus interface the inter-integrat ed circuit (iic) interface provides a philips i 2 c ? compatible interface operating up to 400khz either as a master, a slave, or both with a bootstrap c ontroller (bsc) included. during chip reset, the bootstrap controller can read conf iguration data from an iic co mpatible memory device (e.g ., eeprom). this data can be used to replace the default configurat ion settings provided by the chip. features include: ? two iic channels ? compliant with philips semiconductors i 2 c specification , dated 1995 ? operation at 100khz or 400khz ? byte (8-bit) data ? addresses are 10 or 7 bits ? slave transmit and receive ? master transmit and receive ? multiple bus masters supported ? programmable as master, slave, or master/slave ? boot parameters read from iic attached me mory (port 0) with iic bootstrap controller ? opb slave interface is 32 bits wide serial communication po rt interface (scp/spi) the serial communication port (scp) (also known as the serial peripheral interface or spi) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. the scp is a master on the serial port supporting a three-wire inte rface (receive, transmit, and cl ock), and is a slave on the opb. features include: ? one scp channel, full duplex synchronous ?scp master ? up to 25mhz ? programmable internal loopback capabilities ? multi-master protocol supported ? independent masking of all in terrupts (master collision, tr ansmit fifo overflow, tran smit fifo empty, receive fifo full, receive fifo under flow, receive fifo overflow) ? dynamic control of serial bit rate of data transfer (serial-master mode only) ? data item size for each data transfer under programmer control (4-to-16 bits) ? opb slave interface is 32 bits wide
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 15 preliminary data sheet general purpose i/o (gpio) controller the gpio controller enables multiplexing of module i/o pins wi th multiple functions within the chip. that is, a single package pin can be assigned to multiple i/o functions. which function the pin is as signed to is determined by register bit settings controlled by software. this signif icantly reduces the number of package pins needed to support multiple i/o groups. features include: ? up to 32 gpios available ? gpios are multiplexed with alternate functions ? if not in use for dedicated functions, i/os are available as gpios ? direct control of all functions from registers programmed by means of opb bus master accesses ? time multiplexing of controller outputs to module outputs ? programmable conversion of module outputs to open-dr ain outputs (enables sharing of active low outputs externally) ? time multiplexing of module inputs to controller inputs universal interrupt controller (uic) the universal interrupt controller (uic) provides the co ntrol, status, and communica tions necessary between the various sources of interrupts and the ppc405 processor. features include: ? ten external interrupt sources supported ? generate interrup t on level (high or low) or edge (rising or falling) ? programmable as synchronous (edge-capture or level-se nsitive) or asynchronous (edge- or level-sensitive triggering) ? each interrupt source/bit programmable as critical or non critical ? dcr bus interface is 32 bits wide ? optional interrupt handler vector generation ? programmable vector base address ? programmable vector offset size ? programmable interrupt priority ordering ? programmable polarity for all interrupt types ? interrupts of the same type do not need to be in contiguous bit positions ? status registers provide: current state of all interrupts, current state of enabled interrupts ethernet controller the ethernet support provides one 10/100/1000 mbps interfaces (gmii/mii/rgmii ). features include: ? ansi/ieee std. 802.3 and i eee 802.3u supple ment compliant ? half-duplex and full-duplex support for the following: ? one gigabit media independant interface (gmii) ? one media independant interface (mii) ? one reduced gmii interfaces (rgmii) ? receive and transmit fifos are 16 k bytes with programmable thresholds ? fcs control for transmit/receive packets ? multiple packet handling in transmit and receive fifos ? unicast, multicast, broadcast, and promiscuous address filtering ? two 256-bit hash filters for unicast and multicast frames ? automatic retransmission of collided frames ? runt frame rejection ? programmable inter-frame gap
ppc405exr ? powerpc 405exr embedded processor 16 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet ? ieee 802.3x compliant for frame-based flow control mechanism, including self-a ssembled control frame transmitting) ? wake-on-lan and power-over-internet supported ? programmable internal/ext ernal loopback capabilities ? opb slave (mac) and plb master (mal) interfaces for control and configuration are 32 bits wide ? mal has 128-bit plb master interface for data path. ? extensive error/status vector ge neration for each processed packet ? vlan tag id supported (according to ieee draft 802.3ac/d1.0 standard) ? programmable automatic source address in clusion/replacement for transmit packets ? programmable automatic pad/fcs stripping for receive packets ? programmable vlan tag inclusion/replacement for transmit packets ? half- or full-duplex gmii/rgmii ? jumbo frames support ? memory access layer (m al) provides dma capability to ethernet channel ? interrupt coalescence support for two transmit and two receive channels general purpose timer (gpt) the gpt provides a time base counter and system time rs in addition to those defined in the processor. features include: ? 32-bit time base counter driven by the opb clock ? seven 32-bit compare timers jtag features include: ? ieee 1149.1 te st access port ? jtag boundary scan description language (bsdl) refer to http://www.amcc.com/embedded/partners for a list of amcc partners supplying probes for use with the jtag interface.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 17 preliminary data sheet figure 2. package 27mm, 388-ball epbga bottom view a 1.0 basic 0.60 0.1 solderball x 388 27.0 27.0 b c d e f g h j k l m aa n p r t u v w y ab 01 03 05 07 09 11 13 15 17 19 02 04 06 08 10 12 14 16 18 21 20 22 25.0 0.3 min pcb substrate epoxy mold compound 2.65 max ? ppc405exr part number 1ywwbzzzzz lot number 23 24 25 26 ac ad ae af top view notes: 1. all dimensions are in mm. gold gate release corresponds to a01 ball location 2. package conforms to jedec ms-034c logo view 3. package available in leaded or lead-free versions side view
ppc405exr ? powerpc 405exr embedded processor 18 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet signal lists the following table lists all the external signals in alphab etical order and shows the ball (pin) number on which the signal appears. shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. signals that have different functions for different modes with the same function are separated by commas. shared signals appear alphabetically multiple times in th e list?once for each signal name on the ball. the page column indicates the page within the table ?signal function al description? on page 41 on which the signals in the indicated interface group begin. table 3. signals listed alphabetically (sheet 1 of 14) signal name ball interface group page agnd k01 power 47 agnd l04 agnd p04 agnd r01 ahv dd m04 power 47 ahv dd r04 av dd j03 power 47 av dd k04 av dd m01 av dd n03 av dd n04 av dd p01 av dd t01 ba0 ad22 ddr 2/1 sdram 45 ba1 af24 ba2 ae24 banksel0 af21 ddr 2/1 sdram 45 banksel1 ae20 busreq[gpio27][dmaeot3][irq5] b03 external bus master 44 cas af20 ddr 2/1 sdram 45 dm0 m25 ddr 2/1 sdram 45 dm1 t26 dm2 ad16 dm3 ad13 dm4 y26 [dmaack0]peraddr07[ts1] j26 dma 44 [dmaack1]gpio31[irq0] d01 [dmaack2][holdreq]gpio22 b05 [dmaack3][extack ]gpio25[irq3] c04 [dmaeot0][peraddr05]gpio26[ts3] k26 dma 44 [dmaeot1]gpio29[irq2] d03 [dmaeot2][extreq ]gpio24[irq4] a03 [dmaeot3][busreq]gpio27[irq5] b03 [dmareq0]peraddr06[ts2] k25 dma 44 [dmareq1]gpio30[irq1] d02 [dmareq2][holdack]gpio23 c05 [dmareq3]peraddr08[ts0] j25
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 19 preliminary data sheet dqs0 m26 ddr 2/1 sdram 45 dqs1 t25 dqs2 ae16 dqs3 ae12 dqs4 y25 eagnd ae07 power 47 eav dd ae08 ecc0 v24 ddr 2/1 sdram 45 ecc1 w24 ecc2 ab26 ecc3 ab25 ecc4 v25 ecc5 w25 ecc6 aa26 ecc7 aa25 eov dd d12 power 47 eov dd t12 eov dd ac05 eov dd ab04 eov dd ac07 eov dd ac08 [extack ]gpio25[dmaack3][irq3] c04 external bus master 44 [extreq ]gpio24[dmaeot2][irq4] a03 extreset b19 table 3. signals listed alphabetically (sheet 2 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 20 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet gmccd ad04 ethernet 41 gmccrs af04 gmcgtxclk, gmc0txclk ae04 gmcmdclk ae03 gmcmdio af02 gmcrefclk ad07 gmcrxclk, gmc0rxclk ad09 gmcrxd0, gmc0rxd0 ac11 gmcrxd1, gmc0rxd1 ae10 gmcrxd2, gmc0rxd2 ad10 gmcrxd3, gmc0rxd3 af09 gmcrxd4 ae09 gmcrxd5 af07 gmcrxd6 af06 gmcrxd7 ae06 gmcrxdv, gmc0rxctl ae05 gmcrxer af05 gmctxclk ac06 gmctxd0, gmc0txd0 ae01 gmctxd1, gmc0txd1 ad02 gmctxd2, gmc0txd2 ad01 gmctxd3, gmc0txd3 ac03 gmctxd4 ac02 gmctxd5 ac01 gmctxd6 ab03 gmctxd7 ab02 gmctxen, gmc0txctl ad05 gmctxer af03 table 3. signals listed alphabetically (sheet 3 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 21 preliminary data sheet gnd a01 power 47 gnd a08 gnd a13 gnd a19 gnd a26 gnd b01 gnd b02 gnd b25 gnd c01 gnd c02 gnd c03 gnd c24 gnd d04 gnd d09 gnd d14 gnd d18 gnd d23 gnd e01 gnd e03 gnd h01 gnd h26 gnd j04 gnd j23 gnd k24 gnd l11 gnd l13 gnd l16 gnd m12 gnd m13 gnd m14 gnd m15 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n26 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p23 table 3. signals listed alphabetically (sheet 4 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 22 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet gnd r12 power 47 gnd r13 gnd r14 gnd r15 gnd t11 gnd t14 gnd t16 gnd u01 gnd u02 gnd v04 gnd v23 gnd w01 gnd w26 gnd ab01 gnd ac04 gnd ac09 gnd ac13 gnd ac18 gnd ac23 gnd ad03 gnd ad24 gnd ae02 gnd ae25 gnd af01 gnd af08 gnd af14 gnd af19 gnd af26 table 3. signals listed alphabetically (sheet 5 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 23 preliminary data sheet gpio00[perdatapar0] a16 system 43 gpio01[perdatapar1] b12 gpio02[perdatapar2] c09 gpio03[perdatapar3] b04 gpio04[perdata20][usb2data4] c13 gpio05[perdata21][usb2data5] b09 gpio06[perdata22][usb2data6] c12 gpio07[perdata23][usb2data7] d11 gpio08[percs1 ][nfce1 ][irq7] c20 gpio09[percs2 ][nfce2 ][irq8] a21 gpio10[percs3 ][nfce3 ][irq9] b20 gpio11[irq6] h03 gpio12[perdata16][usb2data0] c11 gpio13[perdata17][usb2data1] b08 gpio14[perdata18][usb2data2] a10 gpio15[perdata19][usb2data3] b10 gpio16[uart0dcd ][uart1cts ]f04 gpio17[uart0dsr ][uart1rts ]f02 gpio18[uart0cts ]g02 gpio19[uart0rts ]g01 gpio20[uart0dtr ][uart1tx] f03 gpio21[uart0ri ][uart1rx] f01 gpio22[holdreq][dmaack2] b05 gpio23[holdack][dmareq2] c05 gpio24[extreq ][dmaeot2][irq4] a03 gpio25[extack ][dmaack3][irq3] c04 gpio26[peraddr05][dmaeot0][ts3] k26 gpio27[busreq][dmaeot3][irq5] b03 gpio28 u03 gpio29[irq2][dmaeot1] d03 gpio30[irq1][dmareq1] d02 gpio31[irq0][dmaack1] d01 halt a02 system 43 [holdack]gpio23[dmareq2] c05 external bus master 44 [holdreq]gpio22[dmaack2] b05 iic0sdata aa01 iic 41 iic0sclk y03 iic1sdata[scpdo] aa04 iic1sclk[scpclkout] aa02 table 3. signals listed alphabetically (sheet 6 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 24 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet [irq0]gpio31[dmaack1] d01 interrupts 42 [irq1]gpio30[dmareq1] d02 [irq2]gpio29[dmaeot1] d03 [irq3][extack ]gpio25[dmaack3] c04 [irq4][extreq ]gpio24[dmaeot2] a03 [irq5][busreq]gpio27[dmaeot3] b03 [irq6]gpio11 h03 [irq7][percs1 ][nfce1 ]gpio08 c20 [irq8][percs2 ][nfce2 ]gpio09 a21 [irq9][percs3 ][nfce3 ]gpio10 b20 memaddr00 ae21 ddr2/1 sdram 45 memaddr01 ad20 memaddr02 af22 memaddr03 ae22 memaddr04 af23 memaddr05 ad21 memaddr06 ac21 memaddr07 ae23 memaddr08 ae26 memaddr09 ad25 memaddr10 ad26 memaddr11 ac24 memaddr12 ab24 memaddr13 ac25 memaddr14 ac26 memclken y24 ddr2/1 sdram 45 memclkout0 aa23 memclkout0 aa24 table 3. signals listed alphabetically (sheet 7 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 25 preliminary data sheet memdata00 m24 ddr2/1 sdram 45 memdata01 n24 memdata02 p25 memdata03 p24 memdata04 l25 memdata05 l26 memdata06 n25 memdata07 p26 memdata08 r24 memdata09 t24 memdata10 v26 memdata11 u24 memdata12 r25 memdata13 r26 memdata14 u26 memdata15 u25 memdata16 ae17 memdata17 af17 memdata18 ae15 memdata19 af15 memdata20 af18 memdata21 ad17 memdata22 af16 memdata23 ad15 memdata24 ae13 memdata25 af12 memdata26 af10 memdata27 ad11 memdata28 ae14 memdata29 af13 memdata30 af11 memdata31 ae11 memfbd ad23 ddr2/1 sdram 45 memfbr af25 memodt0 ad18 memodt1 ae18 table 3. signals listed alphabetically (sheet 8 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 26 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet [nfale]perdata30 c06 nand flash 45 [nfce0 ]percs0 b21 [nfce1 ][percs1 ]gpio08[irq7] c20 [nfce2 ][percs2 ]gpio09[irq8] a21 [nfce3 ][percs3 ]gpio10[irq9] b20 [nfcle]perdata29 a06 [nfdata00]perdata00 c18 [nfdata01]perdata01 b18 [nfdata02]perdata02 c17 [nfdata03]perdata03 a18 [nfdata04]perdata04 d16 [nfdata05]perdata05 b17 [nfdata06]perdata06 c16 [nfdata07]perdata07 b16 [nfdata08]perdata08 a17 [nfdata09]perdata09 b15 [nfdata10]perdata10 c15 [nfdata11]perdata11 a15 [nfdata12]perdata12 b14 [nfdata13]perdata13 a14 [nfdata14]perdata14 c14 [nfdata15]perdata15 b13 [nfrdybusy ]perdata31 a04 [nfren ]perdata27 a05 [nfwen ]perdata28 c08 ov dd d05 power 47 ov dd d07 ov dd d08 ov dd d13 ov dd d19 ov dd d20 ov dd d22 ov dd e04 ov dd e23 ov dd g04 ov dd g23 ov dd h23 ov dd l12 ov dd l15 ov dd m11 ov dd m16 ov dd r11 ov dd v03 ov dd w04 ov dd y04 table 3. signals listed alphabetically (sheet 9 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 27 preliminary data sheet pcie0atb l03 pci express 42 pcie0clkc l01 pcie0clkt l02 pcie0rext m03 pcie0rextg m02 pcie0rx j01 pcie0rx j02 pcie0tx k02 pcie0tx k03 [peraddr05]gpio26[ts3][dmaeot0] k26 external peripheral 44 peraddr06[ts2][dmareq0] k25 peraddr07[ts1][dmaack0] j26 peraddr08[ts0][dmareq3] j25 peraddr09[ts1e] h25 peraddr10[ts0e] j24 peraddr11[ts1o] g26 peraddr12[ts0o] h24 peraddr13 g25 peraddr14 f26 peraddr15 e26 peraddr16 f25 peraddr17 g24 peraddr18 e25 peraddr19 d26 peraddr20 f24 peraddr21 c26 peraddr22 d25 peraddr23 f23 peraddr24 e24 peraddr25 c25 peraddr26 d24 peraddr27 b26 peraddr28 a25 peraddr29 b24 peraddr30 c23 peraddr31 c22 perblast d21 external peripheral 44 perclk a20 percs0 [nfce0 ]b21 external peripheral 44 [percs1 ][nfce1 ]gpio08[irq7] c20 [percs2 ][nfce2 ]gpio09[irq8] a21 [percs3 ][nfce3 ]gpio10[irq9] b20 table 3. signals listed alphab etically (sheet 10 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 28 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet perdata00[nfdata00] c18 external peripheral 44 perdata01[nfdata01] b18 perdata02[nfdata02] c17 perdata03[nfdata03] a18 perdata04[nfdata04] d16 perdata05[nfdata05] b17 perdata06[nfdata06] c16 perdata07[nfdata07] b16 perdata08[nfdata08] a17 perdata09[nfdata09] b15 perdata10[nfdata10] c15 perdata11[nfdata11] a15 perdata12[nfdata12] b14 perdata13[nfdata13] a14 perdata14[nfdata14] c14 perdata15[nfdata15] b13 [perdata16]gpio12[usb2data0] c11 [perdata17]gpio13[usb2data1] b08 [perdata18]gpio14[usb2data2] a10 [perdata19]gpio15[usb2data3] b10 [perdata20]gpio04[usb2data4] c13 [perdata21]gpio05[usb2data5] b09 [perdata22]gpio06[usb2data6] c12 [perdata23]gpio07[usb2data7] d11 perdata24[usb2dir] a07 perdata25[usb2stop] b07 perdata26[usb2next] b06 perdata27[nfren ]a05 perdata28[nfwen ]c08 perdata29[nfcle] a06 perdata30[nfale] c06 perdata31[nfrdybusy ]a04 [perdatapar0]gpio00 a16 external peripheral 44 [perdatapar1]gpio01 b12 [perdatapar2]gpio02 c09 [perdatapar3]gpio03 b04 pererr c19 external peripheral 44 peroe a24 perready b11 perrw b23 perwbe0 a23 external peripheral 44 perwbe1 c21 perwbe2 b22 perwbe3 a22 psrouser a09 system 43 ras ad19 ddr 2/1 sdram 45 table 3. signals listed alph abetically (sheet 11 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 29 preliminary data sheet reserved n01 other 47 reserved n02 reserved p02 reserved p03 reserved r02 reserved r03 reserved t02 reserved t03 reserved t04 reserved ad12 sagnd a11 power 47 sav dd a12 scpclkout[iic1sclk] aa02 serial communication port 46 scpdi aa03 scpdo[iic1sdata] aa04 sv dd n23 power 47 sv dd r16 sv dd t15 sv dd w23 sv dd y23 sv dd ab23 sv dd ac19 sv dd ac20 sv dd ac22 sv dd ad14 s vref 1a ac14 ddr2/1 sdram 45 s vref 1b t23 s vref 2a ac16 s vref 2b l23 sysclk c10 system 43 syserr ad06 sysreset ad08 tck v02 jtag 42 tdi w02 tdo w03 testen y02 system 43 tmrclk d06 tms v01 jtag 42 trcclk l24 trace 43 trst y01 jtag 42 [ts0]peraddr08[dmareq3] j25 trace 43 [ts1]peraddr07[dmaack0] j26 [ts2]peraddr06[dmareq0] k25 [ts3][peraddr05]gpio26[dmaeot0] k26 table 3. signals listed alphab etically (sheet 12 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 30 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet [ts0e]peraddr10 j24 trace 43 [ts0o]peraddr12 h24 [ts1e]peraddr09 h25 [ts1o]peraddr11 g26 [uart0cts ]gpio18 g02 uart peripheral 46 [uart0dcd ][uart1cts ]gpio16 f04 [uart0dsr ][uart1rts ]gpio17 f02 [uart0dtr ][uart1tx]gpio20 f03 [uart0ri ][uart1rx]gpio21 f01 [uart0rts ]gpio19 g01 uart0rx g03 uart0tx h02 [uart1cts ][uart0dcd ]gpio16 f04 uart peripheral 46 [uart1rts ][uart0dsr ]gpio17 f02 [uart1rx][uart0ri ]gpio21 f01 [uart1tx][uart0dtr ]gpio20 f03 uartserclk e02 uart peripheral 46 usb2clk c07 usb 2.0 46 [usb2data0][perdata16]gpio12 c11 usb 2.0 46 [usb2data1][perdata17]gpio13 b08 [usb2data2][perdata18]gpio14 a10 [usb2data3][perdata19]gpio15 b10 [usb2data4][perdata20]gpio04 c13 [usb2data5][perdata21]gpio05 b09 [usb2data6][perdata22]gpio06 c12 [usb2data7][perdata23]gpio07 d11 [usb2dir]perdata24 a07 usb 2.0 46 [usb2next]perdata26 b06 [usb2stop]perdata25 b07 table 3. signals listed alphab etically (sheet 13 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 31 preliminary data sheet v dd d10 power 47 v dd d15 v dd d17 v dd h04 v dd k23 v dd l14 v dd m23 v dd n11 v dd p16 v dd r23 v dd t13 v dd u04 v dd u23 v dd ac10 v dd ac12 v dd ac15 v dd ac17 we ae19 ddr2/1 sdram 45 table 3. signals listed alphab etically (sheet 14 of 14) signal name ball interface group page
ppc405exr ? powerpc 405exr embedded processor 32 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet in the following table, only the default signal name is show n for each ball. shared balls are marked with an asterisk (*). to determine what signals or functions are shared on those balls, look up the default signal name in ?signals listed alphabetically? on page 18. the following table lists the signals by ball assignment. table 4. signals listed by ball assignment (sheet 1 of 7) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 gnd c01 gnd d01 gpio31 * a02 halt b02 gnd c02 gnd d02 gpio30 * a03 gpio24 * b03 gpio27 * c03 gnd d03 gpio29 * a04 perdata31 * b04 gpio03 * c04 gpio25 * d04 gnd a05 perdata27 * b05 gpio22 * c05 gpio23 * d05 ov dd a06 perdata29 * b06 perdata26 * c06 perdata30 * d06 tmrclk a07 perdata24 * b07 perdata25 * c07 usb2clk d07 ov dd a08 gnd b08 gpio13 * c08 perdata28 * d08 ov dd a09 psrouser b09 gpio05 * c09 gpio02 * d09 gnd a10 gpio14 * b10 gpio15 * c10 sysclk d10 v dd a11 sagnd b11 perready c11 gpio12 * d11 gpio07 * a12 sav dd b12 gpio01 * c12 gpio06 * d12 eov dd a13 gnd b13 perdata15 * c13 gpio04 * d13 ov dd a14 perdata13 * b14 perdata12 * c14 perdata14 * d14 gnd a15 perdata11 * b15 perdata09 * c15 perdata10 * d15 v dd a16 gpio00 * b16 perdata07 * c16 perdata06 * d16 perdata04 * a17 perdata08 * b17 perdata05 * c17 perdata02 * d17 v dd a18 perdata03 * b18 perdata01 * c18 perdata00 * d18 gnd a19 gnd b19 extreset c19 pererr d19 ov dd a20 perclk b20 gpio10 * c20 gpio08 * d20 ov dd a21 percs2 * b21percs0 * c21 perwbe1 d21 perblast a22 perwbe3 b22 perwbe2 c22 peraddr31 d22 ov dd a23 perwbe0 b23 perrw c23 peraddr30 d23 gnd a24 peroe b24 peraddr29 c24 gnd d24 peraddr26 a25 peraddr28 b25 gnd c25 peraddr25 d25 peraddr22 a26 gnd b26 peraddr27 c26 peraddr21 d26 peraddr19
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 33 preliminary data sheet e01 gnd f01 gpio21 * g01 gpio19 * h01 gnd e02 uartserclk f02 gpio17 * g02 gpio18 * h02 uart0tx * e03 gnd f03 gpio20 * g03 uart0rx * h03 gpio11 * e04 ov dd f04 gpio16 * g04 ov dd h04 v dd e05 no ball f05 no ball g05 no ball h05 no ball e06 no ball f06 no ball g06 no ball h06 no ball e07 no ball f07 no ball g07 no ball h07 no ball e08 no ball f08 no ball g08 no ball h08 no ball e09 no ball f09 no ball g09 no ball h09 no ball e10 no ball f10 no ball g10 no ball h10 no ball e11 no ball f11 no ball g11 no ball h11 no ball e12 no ball f12 no ball g12 no ball h12 no ball e13 no ball f13 no ball g13 no ball h13 no ball e14 no ball f14 no ball g14 no ball h14 no ball e15 no ball f15 no ball g15 no ball h15 no ball e16 no ball f16 no ball g16 no ball h16 no ball e17 no ball f17 no ball g17 no ball h17 no ball e18 no ball f18 no ball g18 no ball h18 no ball e19 no ball f19 no ball g19 no ball h19 no ball e20 no ball f20 no ball g20 no ball h20 no ball e21 no ball f21 no ball g21 no ball h21 no ball e22 no ball f22 no ball g22 no ball h22 no ball e23 ov dd f23 peraddr23 g23 ov dd h23 ov dd e24 peraddr24 f24 peraddr20 g24 peraddr17 h24 peraddr12 * e25 peraddr18 f25 peraddr16 g25 peraddr13 h25 peraddr09 * e26 peraddr15 f26 peraddr14 g26 peraddr11 * h26 gnd table 4. signals listed by ball assignment (sheet 2 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor 34 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet j01 pcie0rx k01 agnd l01 pcie0clkc m01 av dd j02 pcie0rx k02 pcie0tx l02 pcie0clkt m02 pcie0rextg j03 av dd k03 pcie0tx l03 pcie0atb m03 pcie0rext j04 gnd k04 av dd l04 agnd m04 ahv dd j05 no ball k05 no ball l05 no ball m05 no ball j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 no ball l10 no ball m10 no ball j11 no ball k11 no ball l11 gnd m11 ov dd j12 no ball k12 no ball l12 ov dd m12 gnd j13 no ball k13 no ball l13 gnd m13 gnd j14 no ball k14 no ball l14 v dd m14 gnd j15 no ball k15 no ball l15 ov dd m15 gnd j16 no ball k16 no ball l16 gnd m16 ov dd j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 no ball k19 no ball l19 no ball m19 no ball j20 no ball k20 no ball l20 no ball m20 no ball j21 no ball k21 no ball l21 no ball m21 no ball j22 no ball k22 no ball l22 no ball m22 no ball j23 gnd k23 v dd l23 s vref 2b m23 v dd j24 peraddr10 * k24 gnd l24 trcclk m24 memdata00 j25 peraddr08 * k25 peraddr06 * l25 memdata04 m25 dm0 j26 peraddr07 * k26 gpio26 * l26 memdata05 m26 dqs0 table 4. signals listed by ball assignment (sheet 3 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 35 preliminary data sheet n01 reserved p01 av dd r01 agnd t01 av dd n02 reserved p02 reserved r02 reserved t02 reserved n03 av dd p03 reserved r03 reserved t03 reserved n04 av dd p04 agnd r04 ahv dd t04 reserved n05 no ball p05 no ball r05 no ball t05 no ball n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 no ball p10 no ball r10 no ball t10 no ball n11 v dd p11 gnd r11 ov dd t11 gnd n12 gnd p12 gnd r12 gnd t12 eov dd n13 gnd p13 gnd r13 gnd t13 v dd n14 gnd p14 gnd r14 gnd t14 gnd n15 gnd p15 gnd r15 gnd t15 sv dd n16 gnd p16 v dd r16 sv dd t16 gnd n17 no ball p17 no ball r17 no ball t17 no ball n18 no ball p18 no ball r18 no ball t18 no ball n19 no ball p19 no ball r19 no ball t19 no ball n20 no ball p20 no ball r20 no ball t20 no ball n21 no ball p21 no ball r21 no ball t21 no ball n22 no ball p22 no ball r22 no ball t22 no ball n23 sv dd p23 gnd r23 v dd t23 s vref 1b n24 memdata01 p24 memdata03 r24 memdata08 t24 memdata09 n25 memdata06 p25 memdata02 r25 memdata12 t25 dqs1 n26 gnd p26 memdata07 r26 memdata13 t26 dm1 table 4. signals listed by ball assignment (sheet 4 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor 36 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet u01 gnd v01 tms w01 gnd y01 trst u02 gnd v02 tck w02 tdi y02 testen u03 gpio28 v03 ov dd w03 tdo y03 iic0sclk u04 v dd v04 gnd w04 ov dd y04 ov dd u05 no ball v05 no ball w05 no ball y05 no ball u06 no ball v06 no ball w06 no ball y06 no ball u07 no ball v07 no ball w07 no ball y07 no ball u08 no ball v08 no ball w08 no ball y08 no ball u09 no ball v09 no ball w09 no ball y09 no ball u10 no ball v10 no ball w10 no ball y10 no ball u11 no ball v11 no ball w11 no ball y11 no ball u12 no ball v12 no ball w12 no ball y12 no ball u13 no ball v13 no ball w13 no ball y13 no ball u14 no ball v14 no ball w14 no ball y14 no ball u15 no ball v15 no ball w15 no ball y15 no ball u16 no ball v16 no ball w16 no ball y16 no ball u17 no ball v17 no ball w17 no ball y17 no ball u18 no ball v18 no ball w18 no ball y18 no ball u19 no ball v19 no ball w19 no ball y19 no ball u20 no ball v20 no ball w20 no ball y20 no ball u21 no ball v21 no ball w21 no ball y21 no ball u22 no ball v22 no ball w22 no ball y22 no ball u23 v dd v23 gnd w23 sv dd y23 sv dd u24 memdata11 v24 ecc0 w24 ecc1 y24 memclken u25 memdata15 v25 ecc4 w25 ecc5 y25 dqs4 u26 memdata14 v26 memdata10 w26 gnd y26 dm4 table 4. signals listed by ball assignment (sheet 5 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 37 preliminary data sheet aa01 iic0sdata ab01 gnd ac01 gmctxd5 ad01 gmctxd2 * aa02 iic1sclk * ab02 gmctxd7 ac02 gmctxd4 ad02 gmctxd1 * aa03 scpdi ab03 gmctxd6 ac03 gmctxd3 * ad03 gnd aa04 iic1sdata * ab04 eov dd ac04 gnd ad04 gmccd aa05 no ball ab05 no ball ac05 eov dd ad05 gmctxen * aa06 no ball ab06 no ball ac06 gmctxclk ad06 syserr aa07 no ball ab07 no ball ac07 eov dd ad07 gmcrefclk aa08 no ball ab08 no ball ac08 eov dd ad08 sysreset aa09 no ball ab09 no ball ac09 gnd ad09 gmcrxclk * aa10 no ball ab10 no ball ac10 v dd ad10 gmcrxd2 * aa11 no ball ab11 no ball ac11 gmcrxd0 * ad11 memdata27 aa12 no ball ab12 no ball ac12 v dd ad12 reserved aa13 no ball ab13 no ball ac13 gnd ad13 dm3 aa14 no ball ab14 no ball ac14 s vref 1a ad14 sv dd aa15 no ball ab15 no ball ac15 v dd ad15 memdata23 aa16 no ball ab16 no ball ac16 s vref 2a ad16 dm2 aa17 no ball ab17 no ball ac17 v dd ad17 memdata21 aa18 no ball ab18 no ball ac18 gnd ad18 memodt0 aa19 no ball ab19 no ball ac19 sv dd ad19 ras aa20 no ball ab20 no ball ac20 sv dd ad20 memaddr01 aa21 no ball ab21 no ball ac21 memaddr06 ad21 memaddr05 aa22 no ball ab22 no ball ac22 sv dd ad22 ba0 aa23 memclkout0 ab23 sv dd ac23 gnd ad23 memfbd aa24 memclkout0 ab24 memaddr12 ac24 memaddr11 ad24 gnd aa25 ecc7 ab25 ecc3 ac25 memaddr13 ad25 memaddr09 aa26 ecc6 ab26 ecc2 ac26 memaddr14 ad26 memaddr10 table 4. signals listed by ball assignment (sheet 6 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor 38 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet ae01 gmctxd0 * af01 gnd ae02 gnd af02 gmcmdio ae03 gmcmdclk af03 gmctxer ae04 gmcgtxclk * af04 gmccrs ae05 gmcrxdv * af05 gmcrxer ae06 gmcrxd7 af06 gmcrxd6 ae07 eagnd af07 gmcrxd5 ae08 eav dd af08 gnd ae09 gmcrxd4 af09 gmcrxd3 * ae10 gmcrxd1 * af10 memdata26 ae11 memdata31 af11 memdata30 ae12 dqs3 af12 memdata25 ae13 memdata24 af13 memdata29 ae14 memdata28 af14 gnd ae15 memdata18 af15 memdata19 ae16 dqs2 af16 memdata22 ae17 memdata16 af17 memdata17 ae18 memodt1 af18 memdata20 ae19 we af19 gnd ae20 banksel1 af20 cas ae21 memaddr00 af21 banksel0 ae22 memaddr03 af22 memaddr02 ae23 memaddr07 af23 memaddr04 ae24 ba2 af24 ba1 ae25 gnd af25 memfbr ae26 memaddr08 af26 gnd table 4. signals listed by ball assignment (sheet 7 of 7) ball signal name ball signal name ball signal name ball signal name
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 39 preliminary data sheet pin group list the following table provides a summary of the number of package pins (balls) associated with each functional interface group. in the table ?signal functional description? on page 41, eac h external signal is listed along with a short description of the signal function. active-l ow signals (for example, halt ) are marked with an overline. see the preceding table, ?signals listed alphabetically? on page 18, for the pin (ball) number to which each signal is assigned. shared pins some signals are shared on the same package pin so that the pin can be used for different functions. in most cases, the signal names shown in this table are not acco mpanied by signal names that might share the same pin. if you need to know what, if any, signals are shared with a particular signal, look up the name in ?signals listed alphabetically? on page 18. it is expect ed that in any single application a particular pin will a lways be programmed to serve the same function. the flexibilit y of sharing allows a single chip to offer a richer pin selection than would otherwise be possible. initialization strapping one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see ?initialization? on page 72). note that the use of these pins for strapping is not considered mult iplexing since the strapping function is not programmable. pull-up and pull-down resistors pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. the recommended pull-up value of 3k to +3.3v and pull- down value of 1k to gnd, applies only to individually terminated signals. to prevent possi ble damage to the device, i/os capable of becoming outputs must never be tied together and terminated through a common resistor. if your system-level test methodology permits, input- only signals can be connected together and terminated through either a common resistor or directly to +3.3v or g nd. when a resistor is used, its value must ensure that the grouped i/os reach a valid logical zero or logical one state when accounting for the total input current into the ppc405exr. table 5. pin groups group no. of pins total signal pins 237 v dd 17 ov dd 20 eov dd 6 sv dd 10 gnd 71 av dd 7 ahv dd 2 sav dd 1 sagnd 1 eav dd 1 eagnd 1 agnd 4 total power pins 141 reserved 10 total pins 388
ppc405exr ? powerpc 405exr embedded processor 40 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet reserved balls the balls marked reserved on this chip are not functional. however, most of the reserved balls cannot be left unconnected. connect the balls shown in the following table as indicated: table 6. non-functional ball connections ball connection n01 gnd n02 gnd p02 open p03 open r02 gnd r03 gnd t02 gnd t03 gnd t04 gnd ad12 open
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 41 preliminary data sheet signal functional descriptions the following table provides a description of the i/o signals on the ppc405exr. table 7. signal functional description (sheet 1 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes ethernet interface gmccd gmii/mii: collision detect. i 3.3v tolerant 2.5v cmos 1, 5 gmccrs gmii/mii: carrier sense. i/o 3.3v tolerant 2.5v cmos 1 gmcgtxclk, gmc0txclk gmii/mii: transmit clock for gmii 1000mbps. rgmii 0: transmit clock. o 3.3v tolerant 2.5v cmos gmcmdclk management data clock. o 3.3v tolerant 2.5v cmos gmcmdio management data i/o. i/o 3.3v tolerant 2.5v cmos gmcrefclk gmii/mii, rgmii: required 125mhz reference clock. i 3.3v tolerant 2.5v cmos receiver 1, 5 gmcrxclk, gmc0rxclk gmii/mii: receive clock. rgmii 0: receive clock. i 3.3v tolerant 2.5v cmos 1, 5 gmcrxd0:3, gmc0rxd0:3 gmii/mii: receive data. rgmii 0: receive data. i 3.3v tolerant 2.5v cmos 1 gmcrxd4:7 gmii/mii: receive data. i 3.3v tolerant 2.5v cmos 1 gmcrxdv, gmc0rxctl gmii/mii: receive data valid. rgmii 0: receive control. i 3.3v tolerant 2.5v cmos 1 gmcrxer gmii/mii: receive error. i 3.3v tolerant 2.5v cmos 1 gmctxclk gmii/mii: transmit clock for 10/100mbps. i 3.3v tolerant 2.5v cmos 1, 5 gmctxd0:3, gmc0txd0:3 gmii/mii: transmit data. rgmii 0: transmit data. o 3.3v tolerant 2.5v cmos gmctxd4:7 gmii/mii: transmit data. o 3.3v tolerant 2.5v cmos gmctxen, gmc0txctl gmii/mii: transmit enable. rgmii 0: transmit control. o 3.3v tolerant 2.5v cmos gmctxer gmii/mii: transmit error. o 3.3v tolerant 2.5v cmos iic interface iic0sclk iic serial clock. i/o 3.3v lvttl 1, 2 iic0sdata iic serial data. i/o 3.3v lvttl 2 iic1sclk iic serial clock. i/o 3.3v lvttl 1 iic1sdata iic serial data. i/o 3.3v lvttl 1
ppc405exr ? powerpc 405exr embedded processor 42 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet pci express interface pcie0atb analog test bus for manufacturing test. na analog pcie0clkc pcie0clkt differential input for external reference clock. i cml 5 pcie0rext pcienrextg external reference resistor. attach a 1.37 k , 1% resistor between rext and rextg to provide the reference for both the bias currents and the impedance calibration circuitry. na analog pcie0rx pcie0rx differential receiver for received serial data. note: input must be dc coupled and biased to 0v common mode. i lvds receiver pcie0tx pcie0tx differential driver for transmitted serial data. note: output must be ac coupled. o lvds driver interrupts interface irq0:2 external interrupt requests. i 3.3v lvttl irq3:5 external interrupt requests. i 3.3v lvttl 1 irq6 external interrupt requests. i 3.3v lvttl irq7:9 external interrupt requests. i 3.3v lvttl 1 jtag interface tck test clock. i 3.3v lvttl 1 tdi test data in. i 3.3v lvttl w/pull-up 1, 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl w/pull-up 1 trst test reset. must be low during power-on reset to initialize the jtag controller and for normal operation of the chip. i 3.3v lvttl w/pull-up 1, 5 table 7. signal functional description (sheet 2 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 43 preliminary data sheet system interface sysclk system input clock. i 3.3v tolerant 2.5v cmos receiver 1 syserr machine check exception has occurred. o 3.3v tolerant 2.5v cmos sysreset main system reset. this signal may be driven by the ppc405exr to cause a board level reset to occur. i/o 3.3v tolerant 2.5v cmos 1, 2 testen test enable. reserved for manufacturing lssd test. i 3.3v lvttl receiver w/pull-down 3 halt external request to stop the processor. i 3.3v lvttl rcvr w/pull-up tmrclk processor timer external input. i 3.3v lvttl receiver w/pull-up gpio00:27 gpio29:31 general purpose i/o. most of the gpio signals are multiplexed with other signals. which signal is c onnected to the external pin depends on the setting of bits in the gpio registers. i/o 3.3v lvttl gpio28 general purpose i/o. most of the gpio signals are multiplexed with other signals. which signal is c onnected to the external pin depends on the setting of bits in the gpio registers. i/o 3.3v tolerant 2.5v cmos psrouser performance screen ring output. use for module characterization and screening only. o3 trace interface trcclk trace interface clock. operates at half the cpu core frequency. o 3.3v lvttl ts0e ts1e even trace execution status. i/o 3.3v lvttl ts0o ts1o odd trace execution status. i/o 3.3v lvttl ts0:3 trace status. i/o 3.3v lvttl table 7. signal functional description (sheet 3 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor 44 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet external peripheral interface peraddr05:31 address bus 5:31. i/o 3.3v lvttl perclk clock output. o 3.3v lvttl percs0 chip selects 0. o 3.3v lvttl 2 percs1:3 chip selects 1:3. i/o 3.3v lvttl 1, 2 perdata00:31 data bus 0:31. i/o 3.3v lvttl perdatapar0:3 data bus parity 0:3. i/o 3.3v lvttl peroe output enable. o 3.3v lvttl 2 perready slave is ready to transfer data. i 3.3v lvttl receiver perblast last transfer of burst access. i/o 3.3v lvttl 1, 4 pererr external bus error. i/o 3.3v lvttl 1, 3 perrw read/write. i/o 3.3v lvttl 1, 2 perwbe0:3 write byte enable 0:3. i/o 3.3v lvttl 1, 2 extreset external reset. o 3.3v lvttl external bus master interface busreq external bus request. o 3.3v lvttl 1 extack external data transfer complete. o 3.3v lvttl 1 extreq external data transfer request. i 3.3v lvttl 1 holdreq external request for bus access. i 3.3v lvttl 1 holdack external request acknowledge. o 3.3v lvttl 1 dma interface dmaack0:1 external peripheral dma acknowledge. o 3.3v lvttl dmaack2:3 external peripheral dma acknowledge. o 3.3v lvttl 1 dmareq0:1 external peripheral dma request. i 3.3v lvttl dmareq2 external peripheral dma request. i 3.3v lvttl 1 dmareq3 external peripheral dma request. i 3.3v lvttl dmaeot0:1 external dma peripheral end-of-transmission. i/o 3.3v lvttl dmaeot2:3 external dma peripheral end-of-transmission. i/o 3.3v lvttl 1 table 7. signal functional description (sheet 4 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 45 preliminary data sheet nand flash interface nfale address latch enable. o 3.3v lvttl nfce0 chip select 0. o 3.3v lvttl nfce1:3 chip selects 1:3. o 3.3v lvttl 1 nfcle command latch enable. o 3.3v lvttl nfdata00:15 data bus i/o 3.3v lvttl nfrdybusy read/busy. if low, indicates that read/erase command is in process. if high, indicates that the command is complete. i 3.3v lvttl nfre read enable. o 3.3v lvttl nfwe write enable. o 3.3v lvttl ddr1/2 sdram interface memdata00:31 memory data. i/o 2.5v (1.8v) sstl2 dr/rcv memaddr00:14 memory address. o 2.5v (1.8v) sstl2 dr/rcv ras row address strobe. o 2.5v (1.8v) sstl2 dr/rcv cas column address strobe. o 2.5v (1.8v) sstl2 dr/rcv memclken clock enable. o 2.5v (1.8v) sstl2 dr/rcv memclkout0 memclkout0 differential ddr sdram clock output. o 2.5v (1.8v) sstl2 dr/rcv memfbd feedback driver. connect directly to memfbr with the minimum trace length. o 2.5v (1.8v) sstl2 dr/rcv memfbr feedback receiver. connect externally to memfbd. i 2.5v (1.8v) sstl2 dr/rcv memodt0:1 on-die termination. o 2.5v (1.8v) sstl2 dr/rcv dm0:4 write data byte lane mask. dm4 is the byte lane mask for the ecc byte lane. o 2.5v (1.8v) sstl2 dr/rcv dqs0:4 byte lane strobe. dqs4 is the strobe for the ecc lane. i/o 2.5v (1.8v) sstl2 dr/rcv ba0:2 bank address for up to eight banks. o 2.5v (1.8v) sstl2 dr/rcv banksel0:1 bank select for up to two sdram memory banks. o 2.5v (1.8v) sstl2 dr/rcv ecc0:7 ecc check bit byte. i/o 2.5v (1.8v) sstl2 dr/rcv we write enable. o 2.5v (1.8v) sstl2 dr/rcv table 7. signal functional description (sheet 5 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor 46 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet s vref 1a:b s vref 2a:b ddr 1 (ddr2) reference voltage 1 and 2 inputs: minimum +1.15 (+0.825)v nominal +1.25 (+0.9)v maximum +1.35 (0.975)v i 1.25v (0.9v) volt ref receiver serial communication port (scp) interface scpclkout output clock. i/o 3.3v lvttl scpdi data input. i 3.3v lvttl scpdo data output. o 3.3v lvttl uart peripheral interface the uart interface can be configured as follows: 1. one 8-pin 2. two 4-pin 3. two 2-pin (pull up dcd, dsr, cts and rts) 4. one 4-pin and one 2-pin uartserclk serial clock input. i 3.3v lvttl receiver w/pull-up 4 uartncts clear to send. i 3.3v lvttl 1, 6 uartndcd data carrier detect. i 3.3v lvttl 1, 6 uartndsr data set ready. i 3.3v lvttl 1, 6 uartndtr data terminal ready. o 3.3v lvttl 1 uartnri ring indicator. i 3.3v lvttl 1 uartnrts request to send. o 3.3v lvttl 1 uartnrx receive data. i 3.3v lvttl uartntx transmit data. o 3.3v lvttl usb 2.0 interface usb2clk usb clock. i 3.3v lvttl receiver 5 usb2data0:7 parallel data bus. i/o 3.3v lvttl usb2dir data bus direction control. i 3.3v lvttl usb2next next data byte control. when data is being transferred to the phy, the next byte should be sent. when data is being received from the phy, the next byte is available. i 3.3v lvttl usb2stop stop output control. o 3.3v lvttl table 7. signal functional description (sheet 6 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 47 preliminary data sheet power v dd logic supply (+1.2v). na na na ov dd i/o supply (+3.3v). na na na sv dd ddr1/2 sdram supply (+2.5 v or +1.8v) na na na eov dd ethernet i/o supply (+2.5v) na na na gnd ground. na na na sav dd system pll analog supply (+2.5v). na na na sagnd system pll analog ground. na na na eav dd ethernet pll analog supply (+2.5v). na na na eagnd ethernet pll analog ground. na na na av dd pci-express serdes analog supply (+1.2v) na na na ahv dd pci-express serdes pll analog supply (+2.5v). na na na agnd pci-express analog ground (for ahv dd and av dd) . na na na other reserved to avoid noise pickup problems, these balls must be connected in any board design as shown table 6 on page 40. na na na table 7. signal functional description (sheet 7 of 7) notes: 1. receiver input has hysteresis. 2. must pull up. see ?pull-up and pull-down resist ors? on page 39 for recommended termination values. 3. must pull down. see ?pull-up and pull-down resi stors? on page 39 for recommended termination values. 4. if not used, must pull up. 5. if not used, must pull down. 6. strapping input during reset; pull up or pull down as required. signal name description i/o type notes
ppc405exr ? powerpc 405exr embedded processor 48 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet ratings and specifications table 8. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. none of the performance specification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes logic supply voltage (internal logic) v dd 0 to +1.6 v pci-express serdes analog supply voltage av dd 0 to +1.6 v 1 pci-express serdes pll analog supply voltage ahv dd 0 to +2.6 v 1 i/o supply voltage ov dd 0 to +3.6 v sdram ddr1[2] supply voltage sv dd 0 to +2.6 [+1.9] v ethernet i/o supply voltage eov dd 0 to +2.6 v system pll analog supply voltage sav dd 0 to +2.6 v 1 ethernet pll analog supply voltage eav dd 0 to +2.6 v 1 input voltage (3.3v lvttl receivers) v in 0 to +3.6 v storage temperature range t stg ? 55 to +150 c case temperature range under bias t c ? 40 to +120 c junction temperature range t jmax ? 40 to +125 c2 notes: 1. the analog voltages can be derived from the +1.2v and +2.5v supp lies, but must be filtered as shown below before entering th e ppc405exr. use a separate filter for each voltage. this circuit can be used for av dd , ahv dd , sav dd , and eav dd . 2. the device meets all electrical specific ations at a junction temperature, under bias, of 125oc, but part lifetime and reliab ility is reduced. it is recommended that prudent thermal managem ent techniques be used to ma ximize device lifetime. v dd c1 av dd l1 l1 ? murata blm18ag121sn1d c1 ? 0.1 f ceramic agnd gnd
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 49 preliminary data sheet thermal management the following heat sink was used in the above thermal analysis: 26.92mm x 27mm x 11.43mm the heat sink is manufactured by: aavid thermalloy, p/n 62925 table 9. package thermal specifications the ppc405exr is designed to operate within a case temperature range t c defined in ?recommended dc operating conditions? on page 50. thermal resistance values for the epbga packages in a convection environment are as follows: parameter symbol airflow ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 300 (1.52) 400 (2.02) 500 (2.53) 600 (3.03) junction-to-ambient thermal resistance without heat sink ja 18.9 16.6 15.8 15.4 15.0 14.7 14.4 c/w junction-to-ambient thermal resistance with heat sink ja 15.5 12.5 11.4 10.9 10.7 10.5 10.3 c/w resistance value junction-to-case thermal resistance jc 8.96 c/w junction-to-board thermal resistance jb 13.74 c/w notes: 1. values in the table are achieved with the following jedec standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. 2. for a chip mounted on a card with at least one signal and two power planes, the foll owing relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c ? px ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax ? px jc , where t jmax is maximum junction temperat ure and p is power consumption.
ppc405exr ? powerpc 405exr embedded processor 50 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table 10. recommended dc operating conditions (sheet 1 of 2) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage?333mhz & 400mhz v dd +1.1 +1.15 +1.2 v 2 logic supply voltage?533mhz v dd +1.2 +1.25 +1.3 v i/o supply voltage ov dd +3.15 +3.3 +3.45 v sdram ddr1[2] supply voltage sv dd +2.4 [+1.7] +2.5 [+1.8] +2.6 [+1.9] v ethernet i/o supply voltage eov dd +2.4 +2.5 +2.6 v pll analog supply voltage ahv dd sav dd eav dd +2.4 +2.5 +2.6 v analog supply voltage?333mhz & 400mhz av dd +1.1 +1.15 +1.2 v 2 analog supply voltage?533mhz av dd +1.2 +1.25 +1.3 v i/o input low (3.3v lvttl) v il 0+0.8v i/o input high (3.3v lvttl) v ih +2.0 +3.6 v i/o output low (3.3v lvttl) v ol 0+0.4v i/o output high (3.3v lvttl) v oh +2.4 +3.6 v i/o input low (3.3v tol, 2.5v cmos) v il 0+0.7v i/o input high (3.3v tol, 2.5v cmos) v ih +1.7 +3.6 v i/o output low (3.3v tol, 2.5v cmos) v ol 0+0.4v i/o output high (3.3v tol, 2.5v cmos) v oh +2.0 +2.7 v i/o input low ddr1[2] (sstl2) v il ? 0.3 s vref ? 0.18 [0.125] v i/o input high ddr1[2] (sstl2) v ih s vref + 0.18 [0.125] sv dd + 0.3 v i/o output low ddr1[2] (sstl2) v ol see jesd8-9 (jesd8-15a) standard. v i/o output high ddr1[2] (sstl2) v oh see jesd8-9 (jesd8-15a) standard. v input leakage current (no pull-up or pull-down) i il1 01 a input leakage current (with internal pull-down) i il2 0 (lpdl) 200 (mpul) a 1 input leakage current (with internal pull-up) i il3 ? 150 (lpdl) 0 (mpul) a 1
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 51 preliminary data sheet power supply sequence all the ppc405exr i/o designs are power supply sequence independent. there is no requirement that the power supplies power up in any particular order. the following items are power sequence considerations: ? if the logic power (v dd ) is applied before the i/o supply voltages, the i/os include internal supply sequencing circuitry that ensures the output of the receiver connec ted to internal chip logic is 0 until the i/o power is applied. when the logic power supply is on and the i/o power supplies are off, the i/o logic connected to the associated ball neither sinks or sources significant curren t unless influenced by an internal pull-up or pull-down resistor. while the i/o supply is ramping, the state of the i/o balls are not predictable. this power sequence is not destructive to the i/os or internal logi c and does not cause any functional problems. ? if the i/o power is applied before the logic power is a pplied, the output driver output stage (connected to the balls) will come up in an unknown state (d riving 1, driving 0, or tr i-state) until the internal logic voltage is stable within normal operating range. this powe r sequence is not destructive to the i/os or internal logic and does not cause any functional problems. ? external voltage should not be applied to the chip i/o balls before the associated i/o power supply voltage is applied to the chip. ? a chip power down cycle must complete (all i/o supply voltages and v dd are below + 0.4v) before a new power-up cycle is started. ? during a 405ex power-up cycle, the system reset and test reset inputs should be asserted low. system reset and test reset should remain asserted until the system cl ock is stable and then at least 32 system clock times after all power supplies are stable within normal operating range. failure to follow this reset sequence during the power-up cycle might result in unpredictable operation. i/o maximum allowable overshoot (3.3v lvttl and 2.5v/3.3 tolerant cmos) v mao +3.9 v 3, 4 i/o maximum allowable undershoot (3.3v lvttl and 2.5v/3.3 tolerant cmos) v mau ? 0.6 v 3,4 case temperature t c ? 40 +85 c5 notes: 1. lpdl is least positive down level; mpul is most positive up level. 2. can be extended to 1.1v min., 1.2v typ., 1.3v max. wi th an estimated power increase of 130mw at 1.2v nom. 3. maximum duration is 10% of the bus cl ock period. bus clock is as follows: ebc?perclk ethernet?rxclk usb?usb2clk 4. duration of the overshoot is time above v ih max. duration of the undershoot is time below v il min. 5. a 533mhz part running at 400mhz or less can operate up to a case temperature of + 95c. table 10. recommended dc operating conditions (sheet 2 of 2) device operation beyond the conditions specified is not recommended. extended ope ration beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
ppc405exr ? powerpc 405exr embedded processor 52 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table 11. i/o input capacitance parameter symbol maximum unit notes 3.3v lvttl c in1 2.3 pf 2.5v cmos c in2 2.1 pf 2.5/1.8v sstl2 c in3 3.2 pf pci express differential data receiver c in4 1.59 pf pci express differential data transmitter c in5 1.16 pf pci express differential clock receiver c in6 0.188 pf table 12. typical dc power supply requirements with ddr1 sdram frequency (mhz) + 1.2v nom (v dd + av dd ) + 1.8v (not used with ddr1) + 2.5v (sv dd + eov dd + ahv dd + sav dd + eav dd ) + 3.3v (ov dd ) total unit notes + 1.15v + 1.25v) 333 0.97 na na 0.49 0.11 1.57 w 1, 2 400 1.09 na na 0.55 0.11 1.75 w 1, 3 533 na 1.46 na 0.55 0.11 2.12 w 1, 4 notes: 1. typical power is measured on a typical process part at a case temperature of + 85 c at the specified voltages while running linux and test applications that exercise each function with representative traffic (pci express, gigabit ethernet, usb, and security). 2. ddr1 running at 333mhz., plb running at 166mhz. 3. ddr1 running at 400mhz., plb running at 200mhz. 4. ddr1 running at 355mhz., plb running at 177mhz. table 13. maximum dc power supp ly requirements with ddr1 sdram frequency (mhz) + 1.2v nom (v dd + av dd ) + 1.8v (not used with ddr1) + 2.6v (sv dd + eov dd + ahv dd + sav dd + eav dd ) + 3.45v (ov dd ) total unit notes + 1.2v + 1.3v 333 1.89 na na 0.65 0.15 2.69 w 1, 2 400 2.07 na na 0.72 0.15 2.94 w 1, 3 533 na 2.90 na 0.72 0.17 3.79 w 1, 4 notes: 1. maximum power is measured on a best-case process (worst-case power) part at a case temperature of + 85 c at the specified voltages while running linux and test applications that exercise each function with representativ e traffic (pci expres s, gigabit etherne t, usb, and security). 2. ddr1 running at 333mhz., plb running at 166mhz. 3. ddr1 running at 400mhz., plb running at 200mhz. 4. ddr1 running at 355mhz., plb running at 177mhz.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 53 preliminary data sheet table 14. typical dc power supply requirements with ddr2 sdram frequency (mhz) + 1.2v nom (v dd + av dd ) + 1.8v (sv dd ) + 2.5v (sv dd + eov dd + ahv dd + sav dd + eav dd ) + 3.3v (ov dd ) total unit notes + 1.15v + 1.25v 333 0.97 na 0.21 0.18 0.11 1.47 w 1, 2 400 1.09 na 0.26 0.18 0.11 1.64 w 1, 3 533 na 1.46 0.21 0.19 0.11 1.97 w 1, 4 notes: 1. typical power is measured on a typica l process part at a case temperature of + 85 c at the specified voltages while running linux and test applications that exercise each f unction with representative traffic (pci ex press, gigabit ethernet, usb, and security). 2. ddr2 running at 333mhz., plb running at 166mhz. 3. ddr2 running at 400mhz., plb running at 200mhz. 4. ddr2 running at 355mhz., plb running at 177mhz. table 15. maximum dc power supply requirements with ddr2 sdram frequency (mhz) + 1.2v nom (v dd + av dd ) + 1.9v (sv dd ) + 2.6v (sv dd + eov dd + ahv dd + sav dd + eav dd ) + 3.45v (ov dd ) total unit notes + 1.2v + 1.3v 333 1.89 na 0.21 0.26 0.15 2.51 w 1, 2 400 2.07 na 0.22 0.26 0.15 2.70 w 1, 3 533 na 2.90 0.29 0.26 0.17 3.62 w 1, 4 notes: 1. maximum power is measured on a best-case process (worst-case power) part at a case temperature of + 85 c at the specified voltages while running linux and test applications that exercise each function with represent ative traffic (pci express, gigabit etherne t, usb, and security). 2. ddr2 running at 333mhz., plb running at 166mhz. 3. ddr2 running at 400mhz., plb running at 200mhz. 4. ddr2 running at 355mhz., plb running at 177mhz.
ppc405exr ? powerpc 405exr embedded processor 54 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table 16. dc power supply loads with ddr1 sdram parameter symbol typical maximum unit notes v dd ( + 1.2v) active operating current i dd 1192 2220 ma 1 av dd ( + 1.2v) active operating current i add 410ma1 ahv dd ( + 2.5v) active operating current i ahdd 12ma1 ov dd ( + 3.3v) active operating current i odd 35 50 ma 1 sv dd + eov dd ( + 2.5v) active operating current i eosdd 196 235 ma 1 sav dd ( + 2.5v) active operating current i sadd 12ma1 eav dd ( + 2.5v) active operating current i eadd 12ma1 notes: 1. the maximum current values listed above are not guaranteed to be the highest obtainable. thes e values are dependent on many factors including the type of applications running, clock rates, use of internal f unctional capabilities, external interface us age, case temperature, and the power supply voltages. your specific application can produce signif icantly different results. v dd (logic) current and power are primarily dependent on the applicati ons running and the use of internal chip functions (dma, pci express, ethernet, a nd so on). ov dd (i/o) current and power are primarily dependent on the capacit ive loading, frequency, and utiliza tion of the external buses. the information in this table provides det ails about the conditions under which the li sted values were obtained. maximum power is measured on a best-case process (worst-case power) part running at 533mhz with a case temperature of + 85 c and with voltages of v dd = + 1.30v, ov dd = + 3.45v, sv dd = + 2.6v, and eov dd = + 2.6v while running linux and test appl ications that exercise each function with representative traffic (pci express, gigabit ethernet, usb, security). table 17. dc power supply loads with ddr2 sdram parameter symbol typical maximum unit notes v dd (+1.2v) active operating current i dd 1165 2220 ma 1 av dd (+1.2v) active operating current i add 410ma1 ahv dd (+2.5v) active operating current i ahdd 12ma1 ov dd (+3.3v) active operating current i odd 35 50 ma 1 sv dd (+1.8v) active operating current i sdd 145 155 ma 1 eov dd (+2.5v) active operating current i eodd 76 80 ma 1 sav dd (+2.5v) active operating current i sadd 12ma1 eav dd (+2.5v) active operating current i eadd 12ma1 notes: 1. the maximum current values listed above are not guaranteed to be the highest obtainable. thes e values are dependent on many factors including the type of applications running, clock rates, use of internal f unctional capabilities, external interface us age, case temperature, and the power supply voltages. your specific application can produce signif icantly different results. v dd (logic) current and power are primarily dependent on the applicati ons running and the use of internal chip functions (dma, pci express, ethernet, a nd so on). ov dd (i/o) current and power are primarily dependent on the capacit ive loading, frequency, and utiliza tion of the external buses. the information in this table provides det ails about the conditions under which the li sted values were obtained. maximum power is measured on a best-case process (worst-case power) part running at 533mhz with a case temperature of + 85 c and with voltages of v dd = + 1.30v, ov dd = + 3.45v, sv dd = + 2.6v, and eov dd = + 2.6v while running linux and test applications that exercise each function with representative traffic (pci express, gigabit ethernet, usb, security).
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 55 preliminary data sheet power control this chip has power management control to put the follo wing functional units to sleep if not needed. the typical and maximum power consumption for the each of these units is: test conditions clock timing and switching characteristic s are specified in accordance with minimum operating conditions shown in the table ?recommended dc operating conditions? on page 50. for all signals, ac spec ifications are characterized at t c = 85c with the test load shown in the figure to the right. figure 3. clocking waveform table 18. power contribution of functional units functional unit typical maximum units notes ebm/opb 0.006 0.012 w security 0.117 0.230 w nand flash 0.127 0.246 w usb 0.005 0.008 w emac 0.118 0.133 w table 19. system clocking specifications symbol parameter min max units cpu pf c processor clock frequency (must be scf c ) 333.33 533.33 mhz sysclk input scf c frequency 33.33 100 mhz sct cs edge stability (phase jitter, cycle-to-cycle) na 0.1 ns sct ch high time (% of nominal period) 40 60 % sct cl low time (% of nominal period) 40 60 % sc rt rise time na 1 ns note: input slew rate = 1v/ns other clocks vcof c vco frequency 600 1600 mhz plbf c plb frequency 133 200 mhz opbf c opb frequency 66 100 mhz output pin 10pf t cl t ch t c 2.0v 1.5v 0.8v
ppc405exr ? powerpc 405exr embedded processor 56 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet spread spectrum clocking care must be taken if using a spread spectrum clock generator (sscg) with the ppc4 05exr. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is called tracking skew. the pll bandwidth and phase angle determine how much tracking skew exists between the sscg and the pll for a given frequency deviation and modulation frequency. if using an sscg with the ppc405exr the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc405exr with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency de viation must not exceed ? 3%, and the modulation frequency must not exceed 40khz. in some cases, on-board ppc405exr peripherals impose more stringent requirements (see note 1). ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus because this clock tracks the modulation. notes: 1. the serial port baud rates are synchronous to the mo dulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors b egin to occur, assuming that the connected device is running at precise baud rates. if an external serial clock is used, baud rate is unaffected by the modulation. 2. ethernet operation is unaffected. 3. iic operation is unaffected. 4. for pci-e see the pci ex press i/o specifications. caution: the system designer must ensure that any sscg us ed with the ppc405exr meets these requirements and does not adversely affect other aspects of the system.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 57 preliminary data sheet table 20. peripheral interface i/o clock timings (not sdram or pci-e) clock min max units notes gmctxclk frequency 125 125 mhz gmctxclk high time 45% of nominal ? ns gmctxclk low time 55% of nominal ? ns gmcrxclk frequency 125 125 mhz gmcrxclk high time 45% of nominal ? ns gmcrxclk low time 55% of nominal ? ns gmcgtxclk 125 125 mhz gmcmdclk 2.5 25 mhz gmcrefclk 125 125 mhz gmcrefclk edge stability (phase jitte r, cycle-to-cycle) na 0.1 ns gmcrefclk rise time na 1 ns gmcrefclk high time 40% of nominal ? ns gmcrefclk low time 60% of nominal ? ns gmc1rxclk 125 125 mhz gmc1txclk 125 125 mhz uartserclk 1000 / 2t opb1 + 2ns mhz 1 tmrclk na 100 mhz perclk 33 100 mhz tck na 20 mhz usb2clk (60mhz 0.05%) 57.97 60.03 mhz trcclk 66 300 mhz 2 notes: 1. t opb is the period in ns of the opb clock. th e internal opb clock runs at an integral di visor ratio of the frequency of the plb clo ck. the maximum opb clock frequency is 100mhz. 2. trcclk is 1/2 cpu clk. the maximum cpu cl k supported for instruction trace is 400 mhz.
ppc405exr ? powerpc 405exr embedded processor 58 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet figure 4. input setup and hold timing waveform figure 5. output delay and float timing waveform system clock t is t ih min min inputs valid 1.5v 1.5v valid t ov t oh min outputs system clock outputs t of min max max 1.5v 1.5v 1.5v
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 59 preliminary data sheet figure 6. input setup and hold timing waveform for rgmii signals figure 7. output delay and hold timing waveform for rgmii signals gmcnrxclk t is t ih inputs valid valid t is t ih 1.25v 1.25v min min min min rgmii 1000mbps timing is with reference to the raising and falling edge of gmcnrxclk. rgmii 10/100mbps timing is with reference only to the raising edge of gmcnrxclk. valid gmcntxclk outputs t oh t ov float (high-z) high (drive) low (drive) valid valid valid t oh t ov 1.25v min min max max rgmii 1000mbps timing is with reference to the raising and falling edge of gmcntxclk. rgmii 10/100mbps timing is with reference only to the raising edge of gmcntxclk.
ppc405exr ? powerpc 405exr embedded processor 60 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet table 21. i/o specifications notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i oh (min) i ol (min) ethernet gmii interface gmcmdio na na na na 5.51 7.23 async 1 gmccd 2 0 na na async 1 gmccrs 2 0 na na async 1 gmcrxd0:7 1.85 0 na na gmcrxclk 1 gmcrxdv 1.95 0 na na gmcrxclk 1 gmcrxer 1.95 0 na na gmcrxclk 1 gmctxd0:7 2.3 2.0 5.51 7.23 gmcgtxclk 1 gmctxer 2.4 2.0 5.51 7.23 gmcgtxclk 1 gmctxen 2.4 2.0 5.51 7.23 gmcgtxclk 1 ethernet rgmii interface (n = 0 or 1) gmcnrxd0:3 0.7 1 na na gmcnrxclk 1 gmcnrxctl 0.8 1 na na gmcnrxclk 1 gmcntxd0:3 0.5 2.7 5.51 7.23 gmcntxclk 1 gmcntxctl 0.5 2.7 5.51 7.23 gmcntxclk 1 internal peripheral interfaces (not sdram or pci-e) iicnsdata na 10.46 uartncts na na 15.75 10.46 uartnrts na na 15.75 10.46 uartndsr na na 15.75 10.46 uartndcd na na 15.75 10.46 uartndtr na na 15.75 10.46 uartnri na na 15.75 10.46 uartnrx na na na na uartntx na na 15.75 10.46 scpdi na na scpdo na 10.46 usb2data0:7 3.9 0 6.3 2 15.75 10.46 usb2clk usb2dir 3.7 0 6.4 2 na na usb2clk usb2next 3.5 0 na na usb2clk usb2stop 6.4 2 15.75 10.46 usb2clk dma interface dmaack0:3 5.2 1.0 15.75 10.46 perclk dmareq0:3 2.4 1 na na perclk dmaeot0:3 2 1 5.3 1.0 15.75 10.46 perclk interrupts interface irq0:9 15.75 10.46 jtag interface tdi na na tdo 15.75 10.46 tms na na trst na na
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 61 preliminary data sheet system interface gpio00:10 na na na na 11.08 7.37 gpio11:15 na na na na 5.51 7.23 gpio16:27 na na na na 11.08 7.37 gpio28 na na na na 15.75 10.46 gpio29:31 na na na na 11.08 7.37 halt na na na na na na syserr na na na na 5.51 7.23 sysreset na na na na 5.51 7.23 external peripheral interface peraddr05:31 1.8 1 5.3 1 11.08 7.37 perclk percs0:3 5.2 1 11.08 7.37 perclk perdata00:31 2.7 1 5.3 1 11.08 7.37 perclk perdatapar0:3 1.9 1 5.3 1 11.08 7.37 perclk peroe 5.2 1 11.08 7.37 perclk perready 2 1 na na perclk perrw 1.8 1 5.3 1 11.08 7.37 perclk perwbe0:3 1.7 1 5.1 1 11.08 7.37 perclk perblast 2 1 5 1 11.08 7.37 perclk pererr 1.9 1 5.3 1 11.08 7.37 perclk extreset 5.3 1 11.08 7.37 perclk busreq 2.3 1 5.1 1 11.08 7.37 perclk holdreq 2 1 5.2 1 na na perclk holdack 5.2 1 11.08 7.37 perclk extack 2.3 1 5 1 11.08 7.37 perclk extreq 2 1 5.3 na na perclk nfale 5.3 1 11.08 7.37 perclk nfce0:3 5.3 1 11.08 7.37 perclk nfcle 5.3 1 11.08 7.37 perclk nfdata0:15 2.3 1 5.3 1 11.08 7.37 perclk nfrdybusy 1.7 1 na na perclk nfren 5.3 1 11.08 7.37 perclk nfwen 5.3 1 11.08 7.37 perclk table 21. i/o specifications notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i oh (min) i ol (min)
ppc405exr ? powerpc 405exr embedded processor 62 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet ddr 2/1 sdram i/o specifications the ddr sdram controller times its operation using the in ternal plb clock signal and generates memclkout from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout can be advanced with respect to th e plb clock by means of the sdram0_clktr programming register. in a typical system, users advance memclkout by 90 . this depends on the specific application and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the ppc405exr embedded processor user?s manual ). the signals are terminated as indicated in figure 8 for the ddr timing data and output currents in the following sections. figure 8. ddr sdram simulati on signal termination model ddr2 sdram on-die termination impedance setting for all ddr2 applications, the on-die termination (odt) impedance value must be set to 75 ohms in the dimm extended mode register (emr) in order to optimize th e data transmission during memory write operations. 10pf 10pf memclkout0 memclkout0 120 50 30pf addr/ctrl/data/dqs/dm (ddr1) v tt = sov dd /2 ppc405exr addr/ctrl (ddr2) note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design depends on many factors, including the type of memory used and the board layout.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 63 preliminary data sheet ddr sdram write operation the rising edge of memclkout aligns with the first rising edge of the dqs signal on writes as indicated in figure 9 . dqs rising and falling edges are centered on valid data for writes. the data in table 23 is generated by means of simulation and incl udes logic, driver, package rlc, and lengths. values are calculated over best case and worst case processes with speed, junction temperature, and voltage as follows: note: in the following tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditio ns. the timing numbers in the following sections are obtained using a simulation that assumes a model as shown in figure 8 . table 22. ddr sdram output driver specifications signal path output current (ma) i/o h (maximum) i/o l (maximum) write data memdata00:31 10 10 ecc0:7 10 10 dm0:4 10 10 memclkout0 10 10 memaddr00:14 10 10 ba0:2 10 10 ras 10 10 cas 10 10 we 10 10 banksel0:1 10 10 memclken 10 10 dqs0:4 10 10 memodt0:1 10 10 table 23. ddr sdram write operation conditions case process speed junction temperature (c) voltage (v) best fast ? 40 +1.3 worst slow +125 +1.1
ppc405exr ? powerpc 405exr embedded processor 64 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet the following diagram illustrates the relationship among the signals in volved with a ddr write operation. figure 9. ddr sdram write cycle timing note: the timing data in the following tables is based on simulation runs using einstimer. table 24. i/o timing?ddr sdram t ds notes: 1. all of the dqs signals are re ferenced to memclkout0 with the dqs delay line programmed to 1 cycle. 2. clock speed is 200mhz. signal name t ds (ns) minimum maximum dqs0 4 6 dqs1 4 6 dqs2 4 6 dqs3 4 6 dqs4 4 6 dqs memdata plb clk memclkout0 addr/cmd t sa t ha t ds t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout0 t ha = hold time for address and command signals from memclkout0 t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq)
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 65 preliminary data sheet ddr sdram read operation data on a read is edge aligned with dqs. to capture the incoming data on the rising and falling edges, dqs is delayed by the ddr co ntroller in order to center a dqs edge on valid data. progra mmable register s control the delay. ddr sdram memclkout0 and read clock delay in order to accommodate timing variations introduced by memory layout and process, a three-stage data path is used to eliminate metastability and allow data sampling to be adjusted for mini mum latency. figure 10 shows the data read path of a singl e data bit. data entering on the left is captured in the stage 1 flip flops. four flip flops are needed to capture an en tire four beat burst on the ddr interface. the ddr controller only supports burst of four. data captured on the rising edge of dqs is stored in the even numbered flip flops. like wise, data captured on the falling edge of dqs is stored in the odd numbered flips flops. to latch the data in stage 1, a delayed version of dqs is used. initialization software is responsible for tuning the dqs delay timing so that dqs is centered on valid da ta. since there is process variation between parts and possible voltage variations on boards, read tuning is required. fixed dqs delay values should not be used on production systems. the feedback data capture window selects which flip fl op is used to store the data sampled by dqs. each output of this block generates a pulse to an input mult iplexer. the series of four pulses selecting the input multiplexer is initiated by a feedback signal pulse on the input of the feedback data capture window. the ddr controller calculates when to assert the feedback signal based on when the data should be present after a read command. the width of the feedback pulse is the same as ddr 1x cl ock. the internal ddr 1x clock is the same frequency as memclkout0. memclkout0 is slightly delayed relati ve to ddr 1x clock due to the insertion delay of the drivers. table 25. i/o timing?ddr sdram t sa and t ha signal name t sa (ns) minimum t ha (ns minimum) memaddr00:14 1.08 1.12 ba0:2 1.12 1.15 banksel0:1 1.09 1.13 memclken 1.10 1.16 cas 1.10 1.13 ras 1.09 1.12 we 1.08 1.16 table 26. i/o timing?ddr sdram write timing t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 200mhz. 3. the time values in the table include 1/ 4 of a cycle at 200mhz (5ns x 0.25 = 1.25 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 1. 25 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (for example, t sd ? 1.25 + 0.25t cyc ). signal names reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 1.067 0.973 memdata08:15, dm1 dqs1 1.074 0.973 memdata16:23, dm2 dqs2 1.082 0.973 memdata24:31, dm3 dqs3 1.088 0.973 ecc0:7, dm4 dqs4 1.012 0.973
ppc405exr ? powerpc 405exr embedded processor 66 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet the feedback signal to the feedback data capture window is adjusted for propagation delay by the fine/coarse delays and is automatically adjusted for variations in the ddr i/o due to supply voltage and temperature. compensation for driver/receiver variations is accomplis hed by driving and receiving the feedback signal on the external memfbd and memfbr pins. tuning the fine/coa rse delays adjust for propagation delay. when properly tuned, the feedback pulse is aligned to the first dqs in a four beat burst such that the rising edge of dqs is nominally centered on the feedback pulse. software must adjust the pulse using the fine/coarse delays when tuning read dqs delay. note: using minimum trace length, connect memfbd directly to memfbr. the data captured in stage 1 is relative to the dqs ti ming domain and is held for four ddr 1x cycles. stage 2 samples the data in stage 1 attempting to capture the da ta in the ddr 1x domain. th e on-time-sample clock from the stage 2 store block samples the stage 1 data at sample cycle t1, t2, t3 or t4. the sample cycle is either selected by initialization software or can be automatically selected and adjusted by the ddr controller. the stage 1 data is sampled a second time by the over sample cl ock at a delayed sample point. the delay between the on- time-sample and over sample clocks is the over-sampling-guard-band. the feedback pulse is sampled with the data captured by th e first dqs in the four beat burst. a match of one or both of the sample clocks with the feedback pulse is a hi t. the ddr controller based on hits or misses by the on- time sample and over sample clocks adjust the sample cycle in order to track variations in dqs. burst data from a sample hit is passed to stage 3. in stage 3 the data is synchronized to the plb clock do main and eventually driven onto the plb bus. the data captured on the rising and fa lling dqs edges is unpacked into the correc t bit locations on the upper (0:63) and lower (64:127) plb bus. when ecc is enable, ecc checking and corrections is done after stage 3. figure 12 illustrates how the three st age read logic captures the data in th e dqs timing domain and synchronizes it to the plb clock domain. the first dqs of four be at burst is roughly centered on feedback signal pulse.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 67 preliminary data sheet figure 10. ddr sdram read data path for a single data bit ddr sdram read cycle timing the following diagram illustrates the relationship of the signals invo lved with a ddr read operation. plb bus programmed delay package mux read dqs c d ff: flip-flop q2 dqs ddr 1x clock mux memdata (x64+ecc) (x64+ecc) read fifo plb 1x clock stage 2 stage 1 stage 3 ff plb bus [0:63] [64:127] dqs rising dqs falling q3 0 2 coarse delay cycles driver rec memfbd memfbr ext feedback read start feedback data capture window ddr 1x clock stage 2 store oversampling dqs aligned cas lat delay feedback signal gen fine delay t1 t2 t3 t4 fine delay ff ff 3 1 1 0 3 edge sync edge sync upper lower signals pins ff q2_ovs ff feedback signal delay +1 compare ddr 1x clock oversampling clock read latency adjust circuit c d ff ff adjust ff q3 (guard band) q2 ecc detection and correction if enabled occurs after stage 3 before completing the read on the plb. on-time sample clock (x4 + x1 2 mux mux ecc bits) (x32 bits + x8 bits ecc)
ppc405exr ? powerpc 405exr embedded processor 68 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet figure 11. ddr sdram memory data and dqs in the following example, the data strobes (dqs) and the dat a are shown to be coincident. there is actually a slight skew as specified by the sdram specifications, and t here can be additional skew due to loading and signal routing. it is recommended that the signal le ngth for all of the dqs signals be matched. the following example shows the timing relationship betw een sdram ddr data at the input pin and storing the data in stage 1. table 27. i/o timing?ddr sdram read timing t sd and t hd 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 200mhz. 3. the time values in the table include 1/ 4 of a cycle at 200mhz (5ns x 0.25 = 1.25 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., t sd - 1.25 + 0.25t cyc ). signal names reference signal read data vs dqs set up t sd (ns) read data vs dqs hold t hd (ns) memdata00:07 dqs0 0.27 0.45 memdata08:15 dqs1 0.27 0.45 memdata16:23 dqs2 0.27 0.45 memdata24:31 dqs3 0.27 0.45 ecc0:7 dqs4 0.27 0.45 dqs memdata t sd t hd
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 69 preliminary data sheet figure 12. ddr sdram read cycle timing?example dqs at pin data at pin d0 d2 high low memfbr at pin d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 data out stage 2 d1 d3 ddr 1x clock ddr 2x clock memclkout0 (diff.) data out stage 1 (0) delayed dqs data out stage 1 (2) data out stage 1 (1) ddr 1x clock cycle valid store 1st data t1 t2 t3 t4 oversampling guard band in stage 2
ppc405exr ? powerpc 405exr embedded processor 70 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet pci express (pci-e) i/o specifications the following tables provide the required i/o timing informat ion regarding the use of t he pci express interface on this chip. table 28. pci-e receiver i/o specifications parameter minimum maximum units notes unit interval (ui) 399.88 400.12 ps differential rx peak-peak voltage 175 1200 mv receiver eye time opening 0.4 - ui maximum time delta between median and deviation from median - 0.3 ui rx differential return loss 10 - db common mode rx return loss 6 - db receiver dc common mode impedance 40 60 dc differential impedance 80 120 rx ac common mode voltage - 150 mv dc input cm input impedance during reset or power down 200 - k electrical idle detect threshold 65 125 ns table 29. pci-e reference clock i/o specifications parameter minimum maximum units notes pci_e reference clock frequency (pcienclkc and pcienclkt ) 100 100 mhz 1 accuracy -300 +300 ppm duty cycle 45 55 % peak-to-peak jitter for 1e-6 ber (1 x 10 -6 bit error rate) -86ps3 spread spectrum clock (ssc) frequency 30 33 khz 2 common mode voltage 0 1600 mv differential signal amplitude 200 1600 mv notes: 1. the pci-e reference clock frequency specification does not include +/- 300ppm accuracy specification. 2. the data rate can be modulated from +0.5% to ? 0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding 30khz?33khz. the +/- 600ppm requirement remains which requires the two communcicating ports to be modulated so that they never exceed a total of 600ppm difference. for most implem entations, this requires that both ports have the same bit rate clock source when the data is modulated with an ssc. 3. 1e-6 is the probability that the jitter is greater than 86ps peak-to-peak.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 71 preliminary data sheet table 30. pci-e transmitter i/o specifications parameter minimum maximum units notes unit interval (ui) 399.88 400.12 ps differential p-p tx voltage swing 800 - mv ppd low power differential p-p tx voltage swing 400 - mv ppd tx de-emphasis level ratio -3.0 -4.0 db minimum tx eye width 0.75 - ui maximum time between the jitter median and maximum deviation from the median -0.125ui transmitter rise and fall time 0.125 - ui maximum tx pll bandwidth - 22 mhz minimum tx pll bw for 3db peaking 1.5 - mhz tx ac common mode voltage - 20 mv absolute delta of dc common mode voltage during l0 and electrical idle. 0 100 mv absolute delta of dc common mode voltage between pcientx and pcientx 025mv electrical idle differential peak output voltage 0 20 mv the amount of voltage change allowed during receiver detection - 600 mv transmitter dc common-mode voltage 0 3.6 v transmitter short-circuit current limit - 90 ma minimum time spent in electrical idle 20 - ns maximum time to transition to a va lid electrical idle after sending an eios -8ns maximum transition time to va lid differential signaling after leaving electrical idle -8ns differential return loss 10 - db common mode return loss 6 - db dc differential tx impedance 80 120
ppc405exr ? powerpc 405exr embedded processor 72 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet initialization the following describes the method by which initial chip settings are es tablished when a system reset occurs. strapping when the sysreset input is driven low (system reset), the state of ce rtain i/o pins is read in order to enable default initial conditions before ppc405exr start-up. the actual inst ant of capture is the nearest system clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. the recommended pull-up is 3k to +3.3v, or 10k to +5v. the recommended pull-down is 1k to gnd. these pins are only used for stra p functions during reset. they are used for other signals during normal operation. the following tabl e lists the strapping pins along with their functions and strapping options. the signal names assigned to the pi ns for normal operation appear below the pin number. table 31. strapping pin assignments pin strapping initialization source option f04 (uart0dcd) f02 (uart0dsr) g02 (uart0cts) ebc 8-bit wide rom a 0 0 0 ebc 16-bit wide rom b 0 0 1 ebc 16-bit wide rom c 0 1 0 ebc 8-bit wide nand flash d 0 1 1 ebc 8-bit wide nand flash e 1 0 0 iic rom at address 0xa8 g 1 0 1 ebc 8-bit wide rom f 1 1 0 iic rom at address 0xa4 h 1 1 1 note: see the ppc405exr embedded processor user?s manual for option descriptions and other details regarding the boot process.
ppc405exr ? powerpc 405exr embedded processor revision 1.10 - july 10, 2008 amcc proprietary 73 preliminary data sheet revision log date version contents of modification 06/07/2007 1.00 initial creation of document. 06/28/2007 1.01 updates and corrections. 10/25/2007 1.02 correct amcc phone numbers. change pererr to always pull down. add revised i/o timing figures from 405ex ds. implement doc issues 374 and 382. major updates to ddr sdram section (and other parts of the ds) (doc issue 392). add pci-e i/o specifications. i/o timing values updates. change boot-from-ebc support (doc issue 383). 11/21/2007 1.03 six voltage pins originally labeled sv dd changed to eov dd . s2v dd changed to sv dd . add trcclk to table 20 . 01/04/2008 1.04 implemented document issues 412, 436, and 440. note: automatic change bars now appear on all updates. 01/15/2008 1.05 implemented doc issue 447: supply voltage changes (wider voltage range with increased power consumption). remove common mode voltage specs. change ddr sdram and pci-e specs. 01/16/2008 1.06 correct voltage changes. 02/13/2008 1.07 change frequency spec on analog supply voltage. update sdram write timing. update pcienclk signal description. increase pci-e differential signal amplitude to 1600mv (doc issue 468). 02/15/2008 1.08 change power consumption num bers from estimated to measured.. 05/02/2008 1.09 change number of rgmii interfaces from two to one (doc issue 476). misc updates (doc issue 482). remove gmcmdio timing numbers (doc issue 495). add power sequence information (doc issue 509) change gmcrefclk signal desc ription (doc issue 523) 07/10/2008 1.10 remove pull-up requirement on uartndsr (doc issue 537). updated part numbers, revision level, and pvr. added extended temperature operation of 533mhz part at 400mhz or less. added maximum power for each speed. added some functional unit power consumption figures.
ppc405exr ? powerpc 405exr embedded processor 74 amcc proprietary revision 1.10 - july 10, 2008 preliminary data sheet applied micro circuits corporation 215 moffett park drive, sunnyvale, ca 94089 phone: (408) 542-8600 ? (800) 840-6055 ? fax: (408) 542-8601 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2008 applied micro circuits corporation.
6310 sequence drive, san diego, ca 92121 (858) 450-9333 fax (858) 450-9885 http://www.appliedmicro.com product change notification: 110209-02 update 11/19/09: implementation and first shipment date changed fr om february 13, 2009 to february 13, 2010. product change notification date november 13, 2009 product change title ppc405ex and ppc405exr transition from revision c t o revision d affected part number list all 405ex and 405exr revision c part numbers. see from part numbers in the next section. description of change (part number from/to) from: to: ppc405ex-ssc400t ppc405ex-ssd400t ppc405ex-ssc533t ppc405ex-ssd533t ppc405ex-ssc600t ppc405ex-ssd600t ppc405ex-nsc400t ppc405ex-nsd400t ppc405ex-nsc533t ppc405ex-nsd533t ppc405ex-nsc600t ppc405ex-nsd600t ppc405ex-spc400t ppc405ex-spd400t ppc405ex-spc533t ppc405ex-spd533t ppc405ex-spc600t ppc405ex-spd600t ppc405ex-npc400t ppc405ex-npd400t ppc405ex-npc533t ppc405ex-npd533t ppc405ex-npc600t ppc405ex-npd600t ppc405exr-ssc333t ppc405exr-ssd333t ppc405exr-ssc400t ppc405exr-ssd400t ppc405exr-ssc533t ppc405exr-ssd533t ppc405exr-nsc333t ppc405exr-nsd333t ppc405exr-nsc400t ppc405exr-nsd400t ppc405exr-nsc533t ppc405exr-nsd533t ppc405exr-spc333t ppc405exr-spd333t PPC405EXR-SPC400T ppc405exr-spd400t ppc405exr-spc533t ppc405exr-spd533t ppc405exr-npc333t ppc405exr-npd333t ppc405exr-npc400t ppc405exr-npd400t ppc405exr-npc533t ppc405exr-npd533t description of change errata fixes (reference ppc405ex and ppc405exr erra ta for details.) die revision transition from rev c (rev1.2) to rev d (rev1.3)
6310 sequence drive, san diego, ca 92121 (858) 450-9333 fax (858) 450-9885 http://www.appliedmicro.com reason for change errata fixes. qualification/test data available upon request sample availability date available now implementation date february 13, 2010. after this date, orders of the older version (rev. c) will only be accepted based on available i nventory. first shipment date february 13, 2010 expected customer actions this form is the official notification of this chan ge. please review this pcn carefully. if there are any concerns, please n otify your amcc sales representative, sales manager or field applic ations engineer within 30 days. automatic acceptance of this chang e shall be assumed if no written objection is received. please direct sample requests to your inside sales representative or go to http://www.appliedmicro.com/sales/samplereque st.html contact for inquiries slsmith@amcc.com

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